From WikiChip
Difference between revisions of "amd/k6-2/k6-2e-233afr"
Line 1: | Line 1: | ||
− | {{amd title|K6-2E-233AFR}} | + | {{amd title|K6-2E/233AFR}} |
+ | {{mpu | ||
+ | | name = K6-2E/233AFR | ||
+ | | no image = No | ||
+ | | image = | ||
+ | | image size = | ||
+ | | caption = | ||
+ | | designer = AMD | ||
+ | | manufacturer = AMD | ||
+ | | model number = K6-2E/233AFR | ||
+ | | part number = K6-2E/233AFR | ||
+ | | part number 1 = | ||
+ | | part number 2 = | ||
+ | | part number 3 = | ||
+ | | market = Embedded | ||
+ | | first announced = May, 1999 | ||
+ | | first launched = May, 1999 | ||
+ | | last order = | ||
+ | | last shipment = | ||
+ | |||
+ | | family = K6-2 | ||
+ | | series = K6-2 Desktop | ||
+ | | locked = | ||
+ | | frequency = 233.33 MHz | ||
+ | | bus type = FSB | ||
+ | | bus speed = 66.66 MHz | ||
+ | | bus rate = 66.66 MT/s | ||
+ | | clock multiplier = 3.5 | ||
+ | | cpuid = 58C | ||
+ | |||
+ | | microarch = K6-2 | ||
+ | | platform = Super 7 | ||
+ | | chipset = | ||
+ | | core name = Chomper Extended | ||
+ | | core family = 5 | ||
+ | | core model = 8 | ||
+ | | core stepping = 12 | ||
+ | | process = 0.25 µm | ||
+ | | transistors = 9,300,000 | ||
+ | | technology = CMOS | ||
+ | | die size = 81 mm² | ||
+ | | word size = 32 bit | ||
+ | | core count = 1 | ||
+ | | thread count = 1 | ||
+ | | max cpus = 1 | ||
+ | | max memory = 4 GB | ||
+ | |||
+ | | electrical = Yes | ||
+ | | power = | ||
+ | | v core = 2.2 V | ||
+ | | v core tolerance = 0.1 V | ||
+ | | v io = 3.3675 V | ||
+ | | v io tolerance = 7% | ||
+ | | sdp = | ||
+ | | tdp = | ||
+ | | temp min = | ||
+ | | temp max = | ||
+ | | tjunc min = | ||
+ | | tjunc max = | ||
+ | | tcase min = 0 °C | ||
+ | | tcase max = 70 °C | ||
+ | | tstorage min = -65 °C | ||
+ | | tstorage max = 150 °C | ||
+ | |||
+ | | packaging = Yes | ||
+ | | package 0 = CPGA-321 | ||
+ | | package 0 type = CPGA | ||
+ | | package 0 pins = 321 | ||
+ | | package 0 pitch = 1.27 mm | ||
+ | | package 0 width = 49.53 mm | ||
+ | | package 0 length = 49.53 mm | ||
+ | | package 0 height = 3.27 mm | ||
+ | | socket 0 = Super 7 | ||
+ | | socket 0 type = PGA-321 | ||
+ | | socket 0 2 = Socket 7 | ||
+ | | socket 0 2 type = PGA-321 | ||
+ | }} | ||
'''K6-2E/233AFR''' was a {{arch|32}} [[x86]] {{amd|microarchitectures/k6-2|K6-2}}-based microprocessor designed and manufactured in [[1999]] by [[AMD]]. Manufactured using a [[0.25 µm process]], this MPU operated at 233 MHz and had a [[FSB]] operating at 66 MHz. | '''K6-2E/233AFR''' was a {{arch|32}} [[x86]] {{amd|microarchitectures/k6-2|K6-2}}-based microprocessor designed and manufactured in [[1999]] by [[AMD]]. Manufactured using a [[0.25 µm process]], this MPU operated at 233 MHz and had a [[FSB]] operating at 66 MHz. | ||
Revision as of 06:45, 5 August 2016
Template:mpu K6-2E/233AFR was a 32-bit x86 K6-2-based microprocessor designed and manufactured in 1999 by AMD. Manufactured using a 0.25 µm process, this MPU operated at 233 MHz and had a FSB operating at 66 MHz.
Contents
Cache
- Main article: K6-2 § Cache
L2$ can be 512 KB to 2 MB, depending on manufacturer and motherboard model. L2$ is off-chip.
Cache Info [Edit Values] | ||
L1I$ | 32 KB "KB" is not declared as a valid unit of measurement for this property. |
1x32 KB 2-way set associative |
L1D$ | 32 KB "KB" is not declared as a valid unit of measurement for this property. |
1x32 KB 2-way set associative |
Graphics
This SoC has no integrated graphics processing unit.
Features
- Auto-power down state
- Stop clock state
Documents
DataSheet
- AMD-K6-2E Processor Data Sheet; Publication #22529 Revision B/0, January 2000
Facts about "K6-2E/233AFR - AMD"
l1d$ description | 2-way set associative + |
l1i$ description | 2-way set associative + |