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Difference between revisions of "amd/cores/castle peak"
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|no image=Yes
 
|no image=Yes
 
|developer=AMD
 
|developer=AMD
−
|first announced=2019
+
|manufacturer=TSMC
−
|first launched=2019
+
|manufacturer 2=GlobalFoundries
 +
|first announced=November 7, 2019
 +
|first launched=November 25, 2019
 
|isa=x86-64
 
|isa=x86-64
−
|microarch=Zen + or Zen 2
+
|isa family=x86
 +
|microarch=Zen 2
 +
|chipset=TRX40
 +
|chipset 2=WRX80
 
|word=64 bit
 
|word=64 bit
−
|proc=12 nm or 7 nm
+
|proc=7 nm
 +
|proc 2=12 nm
 
|tech=CMOS
 
|tech=CMOS
−
|package name 1=amd,socket_tr4
+
|clock min=2,700 MHz
 +
|clock max=4,000 MHz
 +
|package name 1=amd,strx4
 +
|package name 2=amd,swrx8
 
|predecessor=Colfax
 
|predecessor=Colfax
 
|predecessor link=amd/cores/colfax
 
|predecessor link=amd/cores/colfax
 +
|successor=Chagall
 +
|successor link=amd/cores/chagall
 
}}
 
}}
−
'''Castle Peak''' is codename for highest-performance enthusiasts [[microprocessors]] from AMD, due to be released in 2019. Castle Peak will be based on either the {{amd|Zen 2|l=arch}} microarchitecture and [[7 nm process]], or the {{amd|Zen+|l=arch}} microarchitecture and [[12 nm process]]. This family serves as a successor to {{\\|Colfax}}.
+
'''Castle Peak''' ('''CPK'''/'''CPKWS''') is the codename for [[AMD]]'s highest-performance enthusiasts [[microprocessors]] serving as a successor to {{\\|Colfax}}, released in late 2019. Castle Peak-based processors are based on the {{amd|Zen 2|l=arch}} microarchitecture and are fabricated on a [[TSMC]] [[7 nm process]].
  
 +
Castle Peak-based microprocessors are branded as 3rd-generation [[Ryzen Threadripper]].
  
−
{{future information}}
+
== Overview ==
 +
Castle Peak chips are a series of high-performance desktop processors designed by [[AMD]] based on their {{amd|Zen 2|l=arch}} microarchitecture.
  
 +
=== Input/Output Interfaces ===
 +
"Castle Peak" processors integrate eight PCIe controllers and four SATA controllers. Workstation (-WX) models have eight 16-lane PCIe Gen 1, 2, 3, 4 (16&nbsp;GT/s) interfaces, each configurable as up to eight x16/x8/x4/x2/x1 wide (e.g. 1x4 + 4x1 + 1x8) links, so 128 lanes total. Some of these lanes are configurable as SATA Gen 1, 2, 3 (6&nbsp;Gb/s) link. Up to 32 SATA ports are available from the processor in total, as well as four USB 3.2 Gen [[wikipedia:USB 3.0#USB 3.2|2×1]] (10&nbsp;Gb/s) ports, and various low speed interfaces. For details see {{amd|Socket sWRX8|l=pack}}.
  
−
== Overview ==
+
On "Castle Peak" {{abbr|HEDT}} processors only one half of these PCIe and SATA resources are available, i.e. 64 PCIe lanes on four 16-lane interfaces and up to 16 SATA ports in total. For details see {{amd|Socket sTRX4|l=pack}}.
−
{{empty section}}
+
 
 +
On Socket sTRX4 and sWRX8 motherboards the PCIe interfaces are generally used for x8 and x16 (electrically) PCIe slots and x4 M.2 NVMe/SATA SSD connectors, leveraging few of the CPU's SATA ports. One x8 PCIe link on the processor is reserved to attach the AMD {{amd|TRX40}} (HEDT) or {{amd|WRX80}} (workstation) chipset which serves as I/O expander. These devices are members of the AMD-500 Series along with the {{amd|X570}} chipset for {{amd|Socket AM4|l=pack}} processors. A notable difference are four additional PCIe lanes available on the X570 as that chipset is attached with an x4 link.
 +
 
 +
Both the TRX40 and WRX80 offer 16 lanes (plus 8-lane CPU link) PCIe Gen 1, 2, 3, 4; 12 SATA Gen 1, 2, 3 ports, eight sharing pins with the PCIe interface and four dedicated; eight USB 3.2 Gen 2 (10&nbsp;Gb/s) ports, and four (TRX40) or five (WRX80) USB 2.0 ports. The chipset PCIe interfaces are generally used for PCIe slots, on-board Ethernet controllers, M.2 NVMe/SATA SSD and M.2 WLAN connectors. An audio interface is not provided by the processor or the chipsets, an audio controller is commonly attached as on-board USB device. The sTRX4/TRX40 platform supports overclocking, the sWRX8/WRX80 platform does not.
  
 
=== Common Features ===
 
=== Common Features ===
−
{{empty section}}
+
All Castle Peak processors have the following:
 +
* Up to 64 cores / 128 threads
 +
* Everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}}
 +
 
 +
HEDT processors:
 +
* 64 PCIe lanes
 +
* Quad-channel Memory
 +
* Up to DDR4-3200 ECC
 +
* Up to 256&nbsp;GiB using eight 32&nbsp;GiB {{abbr|UDIMM}}s (up to 1&nbsp;TiB/channel addressable)<!--AMD-56443-0.92 Table 2-->
 +
 
 +
Workstation processors:
 +
* 128 PCIe lanes
 +
* Octa-channel Memory
 +
* Up to DDR4-3200 ECC
 +
* Up to 2&nbsp;TiB using eight 256&nbsp;GiB {{abbr|LRDIMM}}s or {{abbr|3DS DIMM}}s (up to 1&nbsp;TiB/channel addressable)<!--ibid.-->
  
 
== Castle Peak Processors ==
 
== Castle Peak Processors ==
−
<!-- NOTE:  
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          This table is generated automatically from the data in the actual articles.
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This table is generated automatically from the data in the actual articles.
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          If a microprocessor is missing from the list, an appropriate article for it needs to be
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          created and tagged accordingly.
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created and tagged accordingly.
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Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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          Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
 
 
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{{comp table start}}
 
{{comp table start}}
−
<table class="comptable sortable tc5 tc6">
+
<table class="comptable sortable">
−
{{comp table header|main|10:List of Castle Peak Processors}}
+
{{comp table header|cols|Family|Microarch.|Cores|Threads|L2$|L3$|Base|Turbo|Memory|{{abbr|TDP}}|Socket|Launched|Price|{{abbr|OPN}}}}
−
{{comp table header|cols|Family|Price|Launched|Cores|Threads|TDP|L2$|L3$|Base|Turbo}}
+
{{#ask: [[Category:microprocessor models by amd]] [[core name::Castle Peak]]
 +
|?full page name
 +
|?model number
 +
|?microprocessor family
 +
|?microarchitecture
 +
|?core count
 +
|?thread count
 +
|?l2$ size
 +
|?l3$ size
 +
|?base frequency#GHz
 +
|?turbo frequency#GHz
 +
|?supported memory type
 +
|?tdp
 +
|?package
 +
|?first launched
 +
|?release price
 +
|?part number
 +
|sort=model number
 +
|format=template
 +
|template=proc table 3
 +
|userparam=16
 +
|mainlabel=-
 +
|valuesep=,<br/>
 +
}}
 +
{{comp table count|ask=[[Category:microprocessor models by amd]] [[core name::Castle Peak]]}}
 +
</table>
 +
{{comp table end}}
 +
 
 +
=== SKU Comparison ===
 +
Below are a number of SKU comparison graphs based on their specifications.
 +
 
 +
<div style="float: left; margin: 10px">
 +
{{#ask: [[Category:microprocessor models by amd]] [[core name::Castle Peak]]
 +
|?core count
 +
|?base frequency
 +
|charttitle=Cores vs. Base Frequency
 +
|numbersaxislabel=Frequency (MHz)
 +
|labelaxislabel=Core Count
 +
|height=400
 +
|width=400
 +
|theme=vector
 +
|group=property
 +
|grouplabel=subject
 +
|charttype=scatter
 +
|format=jqplotseries
 +
|mainlabel=-
 +
}}
 +
</div>
 +
 
 +
<div style="float: left; margin: 10px">
 +
{{#ask: [[Category:microprocessor models by amd]] [[core name::Castle Peak]]
 +
|?core count
 +
|?turbo frequency
 +
|charttitle=Cores vs. Turbo Frequency
 +
|numbersaxislabel=Frequency (MHz)
 +
|labelaxislabel=Core Count
 +
|height=400
 +
|width=400
 +
|theme=vector
 +
|group=property
 +
|grouplabel=subject
 +
|charttype=scatter
 +
|format=jqplotseries
 +
|mainlabel=-
 +
}}
 +
</div>
 +
 
 +
<div style="float: left; margin: 10px">
 
{{#ask: [[Category:microprocessor models by amd]] [[core name::Castle Peak]]
 
{{#ask: [[Category:microprocessor models by amd]] [[core name::Castle Peak]]
−
|?full page name
 
−
|?model number
 
−
|?microprocessor family
 
−
|?release price
 
−
|?first launched
 
 
  |?core count
 
  |?core count
−
|?thread count
 
 
  |?tdp
 
  |?tdp
−
  |?l2$ size
+
  |charttitle=Cores vs. TDP
−
  |?l3$ size
+
|numbersaxislabel=TDP (W)
−
  |?base frequency#GHz
+
|labelaxislabel=Core Count
−
  |?turbo frequency#GHz
+
  |height=400
−
  |format=template
+
  |width=400
−
  |template=proc table 3
+
  |theme=vector
−
  |userparam=12
+
  |group=property
 +
|grouplabel=subject
 +
  |charttype=scatter
 +
  |format=jqplotseries
 
  |mainlabel=-
 
  |mainlabel=-
−
|valuesep=,
 
 
}}
 
}}
−
{{comp table count|ask=[[Category:microprocessor models by amd]] [[core name::Castle Peak]]}}
+
</div>
−
</table>
+
 
−
{{comp table end}}
+
<div style="float: left; margin: 10px">
 +
{{#ask: [[Category:microprocessor models by amd]] [[core name::Castle Peak]]
 +
|?turbo frequency
 +
|?tdp
 +
|charttitle=Frequency vs. TDP
 +
|numbersaxislabel=TDP (W)
 +
|labelaxislabel=Frequency (MHz)
 +
|height=400
 +
|width=400
 +
|theme=vector
 +
|group=property
 +
|grouplabel=subject
 +
|charttype=scatter
 +
|format=jqplotseries
 +
|mainlabel=-
 +
}}
 +
</div>
 +
 
 +
{{clear}}
 +
 
 +
== Bibliography ==
 +
* [https://www.amd.com/en/chipsets/str40 "TRX40 Motherboards for 3rd Gen Ryzen™ Threadripper™ processors"] AMD.com.
 +
* [https://www.amd.com/en/chipsets/wrx80 "Socket sWRX WRX80 Motherboards"] AMD.com.
 +
* {{cite techdoc|title=Infrastructure Roadmap for sTRX4 and sWRX8 Processors|publ=AMD|pid=56443|rev=0.92|date=2021-07}}
 +
 
 +
== See also ==
 +
{{amd zen 2 core see also}}

Latest revision as of 13:16, 17 March 2023

Edit Values
Castle Peak
General Info
DesignerAMD
ManufacturerTSMC, GlobalFoundries
IntroductionNovember 7, 2019 (announced)
November 25, 2019 (launched)
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureZen 2
ChipsetTRX40, WRX80
Word Size
8 octets
16 nibbles
64 bit
Process7 nm
0.007 μm
7.0e-6 mm
, 12 nm
0.012 μm
1.2e-5 mm
TechnologyCMOS
Clock2,700 MHz - 4,000 MHz
Packaging
PackagesTRX4, FCLGA-4094 (FC-OLGA)
Dimension75.4 mm
7.54 cm
2.969 in
× 58.5 mm
5.85 cm
2.303 in
× 6.26 mm
0.246 in
Pitch0.87 mm
0.0343 in
× 1 mm
0.0394 in
Contacts4094
SocketsTRX4
PackagesWRX8, FCLGA-4094 (FC-OLGA)
Dimension75.4 mm
7.54 cm
2.969 in
× 58.5 mm
5.85 cm
2.303 in
× 6.26 mm
0.246 in
Pitch0.87 mm
0.0343 in
× 1 mm
0.0394 in
Contacts4094
SocketsWRX8
Succession

Castle Peak (CPK/CPKWS) is the codename for AMD's highest-performance enthusiasts microprocessors serving as a successor to Colfax, released in late 2019. Castle Peak-based processors are based on the Zen 2 microarchitecture and are fabricated on a TSMC 7 nm process.

Castle Peak-based microprocessors are branded as 3rd-generation Ryzen Threadripper.

Overview[edit]

Castle Peak chips are a series of high-performance desktop processors designed by AMD based on their Zen 2 microarchitecture.

Input/Output Interfaces[edit]

"Castle Peak" processors integrate eight PCIe controllers and four SATA controllers. Workstation (-WX) models have eight 16-lane PCIe Gen 1, 2, 3, 4 (16 GT/s) interfaces, each configurable as up to eight x16/x8/x4/x2/x1 wide (e.g. 1x4 + 4x1 + 1x8) links, so 128 lanes total. Some of these lanes are configurable as SATA Gen 1, 2, 3 (6 Gb/s) link. Up to 32 SATA ports are available from the processor in total, as well as four USB 3.2 Gen 2×1 (10 Gb/s) ports, and various low speed interfaces. For details see Socket sWRX8.

On "Castle Peak" HEDT processors only one half of these PCIe and SATA resources are available, i.e. 64 PCIe lanes on four 16-lane interfaces and up to 16 SATA ports in total. For details see Socket sTRX4.

On Socket sTRX4 and sWRX8 motherboards the PCIe interfaces are generally used for x8 and x16 (electrically) PCIe slots and x4 M.2 NVMe/SATA SSD connectors, leveraging few of the CPU's SATA ports. One x8 PCIe link on the processor is reserved to attach the AMD TRX40 (HEDT) or WRX80 (workstation) chipset which serves as I/O expander. These devices are members of the AMD-500 Series along with the X570 chipset for Socket AM4 processors. A notable difference are four additional PCIe lanes available on the X570 as that chipset is attached with an x4 link.

Both the TRX40 and WRX80 offer 16 lanes (plus 8-lane CPU link) PCIe Gen 1, 2, 3, 4; 12 SATA Gen 1, 2, 3 ports, eight sharing pins with the PCIe interface and four dedicated; eight USB 3.2 Gen 2 (10 Gb/s) ports, and four (TRX40) or five (WRX80) USB 2.0 ports. The chipset PCIe interfaces are generally used for PCIe slots, on-board Ethernet controllers, M.2 NVMe/SATA SSD and M.2 WLAN connectors. An audio interface is not provided by the processor or the chipsets, an audio controller is commonly attached as on-board USB device. The sTRX4/TRX40 platform supports overclocking, the sWRX8/WRX80 platform does not.

Common Features[edit]

All Castle Peak processors have the following:

HEDT processors:

  • 64 PCIe lanes
  • Quad-channel Memory
  • Up to DDR4-3200 ECC
  • Up to 256 GiB using eight 32 GiB UDIMMs (up to 1 TiB/channel addressable)

Workstation processors:

  • 128 PCIe lanes
  • Octa-channel Memory
  • Up to DDR4-3200 ECC
  • Up to 2 TiB using eight 256 GiB LRDIMMs or 3DS DIMMs (up to 1 TiB/channel addressable)

Castle Peak Processors[edit]

ModelFamilyMicroarch.CoresThreadsL2$L3$BaseTurboMemoryTDPSocketLaunchedPriceOPN
3960XRyzen ThreadripperZen 2244812 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
3.8 GHz
3,800 MHz
3,800,000 kHz
4.5 GHz
4,500 MHz
4,500,000 kHz
DDR4-3200280 W
280,000 mW
0.375 hp
0.28 kW
sTRX4,
FCLGA-4094		25 November 2019$ 1,399.00
€ 1,259.10
£ 1,133.19
¥ 144,558.67
100-000000010,
100-100000010WOF
3970XRyzen ThreadripperZen 2326416 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
3.7 GHz
3,700 MHz
3,700,000 kHz
4.5 GHz
4,500 MHz
4,500,000 kHz
DDR4-3200280 W
280,000 mW
0.375 hp
0.28 kW
sTRX4,
FCLGA-4094		25 November 2019$ 1,999.00
€ 1,799.10
£ 1,619.19
¥ 206,556.67
100-000000011,
100-100000011WOF
3980XRyzen ThreadripperZen 2489624 MiB
24,576 KiB
25,165,824 B
0.0234 GiB
3.2 GHz
3,200 MHz
3,200,000 kHz
4.5 GHz
4,500 MHz
4,500,000 kHz
DDR4-3200280 W
280,000 mW
0.375 hp
0.28 kW
FCLGA-4094,
sTRX4
3990XRyzen ThreadripperZen 26412832 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
2.9 GHz
2,900 MHz
2,900,000 kHz
4.3 GHz
4,300 MHz
4,300,000 kHz
DDR4-3200280 W
280,000 mW
0.375 hp
0.28 kW
sTRX4,
FCLGA-4094		7 February 2020$ 3,990.00
€ 3,591.00
£ 3,231.90
¥ 412,286.70
100-000000163,
100-100000163WOF
PRO 3945WXRyzen ThreadripperZen 212246 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
4 GHz
4,000 MHz
4,000,000 kHz
4.3 GHz
4,300 MHz
4,300,000 kHz
DDR4-3200280 W
280,000 mW
0.375 hp
0.28 kW
sWRX8,
FCLGA-4094		14 July 2020100-000000168
PRO 3955WXRyzen ThreadripperZen 216328 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
3.9 GHz
3,900 MHz
3,900,000 kHz
4.3 GHz
4,300 MHz
4,300,000 kHz
DDR4-3200280 W
280,000 mW
0.375 hp
0.28 kW
sWRX8,
FCLGA-4094		14 July 2020100-000000167,
100-100000167WOF
PRO 3975WXRyzen ThreadripperZen 2326416 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
3.5 GHz
3,500 MHz
3,500,000 kHz
4.2 GHz
4,200 MHz
4,200,000 kHz
DDR4-3200280 W
280,000 mW
0.375 hp
0.28 kW
sWRX8,
FCLGA-4094		14 July 2020100-000000086,
100-100000086WOF
PRO 3995WXRyzen ThreadripperZen 26412832 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
2.7 GHz
2,700 MHz
2,700,000 kHz
4.2 GHz
4,200 MHz
4,200,000 kHz
DDR4-3200280 W
280,000 mW
0.375 hp
0.28 kW
sWRX8,
FCLGA-4094		14 July 2020100-000000087,
100-100000087WOF
Count: 8

SKU Comparison[edit]

Below are a number of SKU comparison graphs based on their specifications.

Bibliography[edit]

See also[edit]

arrow up 1.svgPower/Performance

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/cores/castle_peak&oldid=101261"
Facts about "Castle Peak - Cores - AMD"
RDF feed
chipsetTRX40 + and WRX80 +
designerAMD +
first announcedNovember 7, 2019 +
first launchedNovember 25, 2019 +
instance ofcore +
isax86-64 +
isa familyx86 +
manufacturerTSMC + and GlobalFoundries +
microarchitectureZen 2 +
nameCastle Peak +
packagesTRX4 +, FCLGA-4094 + and sWRX8 +
process7 nm (0.007 μm, 7.0e-6 mm) + and 12 nm (0.012 μm, 1.2e-5 mm) +
socketsTRX4 + and sWRX8 +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +