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== Overview == | == Overview == | ||
− | Static Random Access Memory (SRAM) is a type of semiconductor memory. It is ''static'' and ''[[volatile memory|volatile]]'', implying data retention persists for as long as the device is powered without any form of a refresh, however, once the power is cut, data will be lost. It is ''[[random access]]'', meaning the next memory location that can be read or written to does not depend on [[sequential access|the last access location]] | + | Static Random Access Memory (SRAM) is a type of semiconductor memory. It is ''static'' and ''[[volatile memory|volatile]]'', implying data retention persists for as long as the device is powered without any form of a refresh, however, once the power is cut, data will be lost. It is ''[[random access]]'', meaning the next memory location that can be read or written to does not depend on [[sequential access|the last access location]]. |
Large blocks of SRAM memory comprise of arrays of individual SRAM blocks called ''cells''. An SRAM cell is capable of storing a single [[bit]] of data for as long as there is power. Likewise, an array of eight SRAM cells can store 1 [[byte]] of data. Arrays of SRAM form the foundation for every | Large blocks of SRAM memory comprise of arrays of individual SRAM blocks called ''cells''. An SRAM cell is capable of storing a single [[bit]] of data for as long as there is power. Likewise, an array of eight SRAM cells can store 1 [[byte]] of data. Arrays of SRAM form the foundation for every | ||
=== Applications === | === Applications === | ||
− | Due to its relative simplicity, SRAM is the most common memory cell found in modern [[microprocessors]]. It is used for various large buffers and caches. Current SoCs allocate a large portion of the die to SRAM. For example, in Intel's first-generation {{intel|Atom}} processors, codename {{intel| | + | Due to its relative simplicity, SRAM is the most common memory cell found in modern [[microprocessors]]. It is used for various large buffers and caches. Current SoCs allocate a large portion of the die to SRAM. For example, in Intel's first-generation {{intel|Atom}} processors, codename {{intel|Bonnel|l=arch}}, 30,644,682 out of the 47,212,207 transistors (65%) were dedicated to the [[level 2 cache]]. In Intel's Itanium 2, codename {{intel|Montecito|l=arch}}, 90% of the 1.72-billion transistors were occupied by SRAM. |
Below are large SRAM blocks highlighted on real-world high-performance microprocessors, showing how much [[silicon]] area, SRAM typically occupies. There are many smaller blocks that were not marked. | Below are large SRAM blocks highlighted on real-world high-performance microprocessors, showing how much [[silicon]] area, SRAM typically occupies. There are many smaller blocks that were not marked. | ||
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=== Operation === | === Operation === | ||
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− | + | == Cells == | |
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− | + | === 4T Cell === | |
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=== 6T Cell === | === 6T Cell === | ||
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=== 8T Cell === | === 8T Cell === | ||
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== Leading-edge SRAM == | == Leading-edge SRAM == |