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{{title|Self-Aligned Contact (SAC)}} | {{title|Self-Aligned Contact (SAC)}} | ||
− | '''Self-Aligned Contact''' ('''SAC''') is a semiconductor process flow technique that adds a protective [[dielectric]] layer over the [[transistor gate]] in order to prevent contact-to-gate shorts. SAC is | + | '''Self-Aligned Contact''' ('''SAC''') is a semiconductor process flow technique that adds a protective [[dielectric]] layer over the [[transistor gate]] in order to prevent contact-to-gate shorts. SAC is used to enable aggressive scaling of the [[contacted poly pitch]] while minimizing [[yield]] loss due to misalignment and partial overlaps of the contacts over the gate. |
== Overview == | == Overview == | ||
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:[[File:cpp scaling with sac.svg|800px]] | :[[File:cpp scaling with sac.svg|800px]] | ||
− | + | == Bibliography == | |
− | + | * Kaizad Mistry, Semicon 2012. | |
− | + | * Auth, Chris, et al. "A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors." VLSI technology (VLSIT), 2012 symposium on. IEEE, 2012. | |
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[[category:transistor gate]] | [[category:transistor gate]] | ||
[[category:front-end-of-line device fabrication]] | [[category:front-end-of-line device fabrication]] |