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{{microarchitecture | {{microarchitecture | ||
|atype=CPU | |atype=CPU | ||
− | |name= | + | |name=Mongoose 4 |
|designer=Samsung | |designer=Samsung | ||
|manufacturer=Samsung | |manufacturer=Samsung | ||
− | |introduction= | + | |introduction=2018 |
|process=8 nm | |process=8 nm | ||
− | + | |isa=ARMv8 | |
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− | |isa=ARMv8 | ||
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|predecessor=M3 | |predecessor=M3 | ||
|predecessor link=samsung/microarchitectures/m3 | |predecessor link=samsung/microarchitectures/m3 | ||
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|successor link=samsung/microarchitectures/m5 | |successor link=samsung/microarchitectures/m5 | ||
}} | }} | ||
− | '''Exynos | + | '''Exynos Mongoose 4''' ('''M4''') is the successor to the {{\\|Mongoose 3}}, an [[8 nm]] [[ARM]] microarchitecture designed by [[Samsung]] for their consumer electronics. |
== Process Technology == | == Process Technology == | ||
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* [[ARMv8.2]] (from [[ARMv8]]) | * [[ARMv8.2]] (from [[ARMv8]]) | ||
** Support for full FP16 scalar extension | ** Support for full FP16 scalar extension | ||
− | ** | + | ** Suppot for integer dot product extension |
* Front end | * Front end | ||
** Larger [[instruction queue]] (48 entries, up from 40) | ** Larger [[instruction queue]] (48 entries, up from 40) | ||
* Back end | * Back end | ||
− | ** LSU | + | ** LSU reorganized |
** Floating-point execution units reorganized | ** Floating-point execution units reorganized | ||
{{expand list}} | {{expand list}} | ||
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=== Block Diagram === | === Block Diagram === | ||
==== Individual Core ==== | ==== Individual Core ==== | ||
− | |||
[[File:mongoose 4 block diagram.svg|900px]] | [[File:mongoose 4 block diagram.svg|900px]] | ||
=== Memory Hierarchy === | === Memory Hierarchy === | ||
* Cache | * Cache | ||
− | ** L1I | + | ** L1I Cache |
*** 64 KiB, 4-way set associative | *** 64 KiB, 4-way set associative | ||
**** 128 B line size | **** 128 B line size | ||
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*** 32 B/cycle bandwidth | *** 32 B/cycle bandwidth | ||
** L3 Cache | ** L3 Cache | ||
− | *** | + | *** 4 MiB, 16-way set associative |
**** 1 MiB slice/core | **** 1 MiB slice/core | ||
*** Exlusive of L2 | *** Exlusive of L2 | ||
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*** 80 outstanding transactions | *** 80 outstanding transactions | ||
− | + | Mongoose 1 TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB). | |
* TLBs | * TLBs | ||
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==== Memory subsystem ==== | ==== Memory subsystem ==== | ||
− | + | {{empty section}} | |
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− | {{ | ||
− | == All | + | == All M3 Processors == |
<!-- NOTE: | <!-- NOTE: | ||
This table is generated automatically from the data in the actual articles. | This table is generated automatically from the data in the actual articles. | ||
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{{comp table start}} | {{comp table start}} | ||
<table class="comptable sortable tc5 tc6 tc7"> | <table class="comptable sortable tc5 tc6 tc7"> | ||
− | {{comp table header|main| | + | {{comp table header|main|7:List of M4-based Processors}} |
− | {{comp table header|main|5:Main processor|2:Integrated Graphics | + | {{comp table header|main|5:Main processor|2:Integrated Graphics}} |
− | {{comp table header|cols|Family|Launched|Arch|Cores|%Frequency|GPU|%Frequency | + | {{comp table header|cols|Family|Launched|Arch|Cores|%Frequency|GPU|%Frequency}} |
− | {{#ask: [[Category:microprocessor models by samsung]] [[microarchitecture:: | + | {{#ask: [[Category:microprocessor models by samsung]] [[microarchitecture::Mongoose 4]] |
|?full page name | |?full page name | ||
|?model number | |?model number | ||
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|?integrated gpu | |?integrated gpu | ||
|?integrated gpu base frequency | |?integrated gpu base frequency | ||
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|format=template | |format=template | ||
|template=proc table 3 | |template=proc table 3 | ||
− | |userparam= | + | |userparam=9 |
|mainlabel=- | |mainlabel=- | ||
|valuesep=, | |valuesep=, | ||
}} | }} | ||
− | {{comp table count|ask=[[Category:microprocessor models by samsung]] [[microarchitecture:: | + | {{comp table count|ask=[[Category:microprocessor models by samsung]] [[microarchitecture::Mongoose 4]]}} |
</table> | </table> | ||
{{comp table end}} | {{comp table end}} |
Facts about "Exynos M4 - Microarchitectures - Samsung"
codename | Cheetah + |
core count | 4 + |
designer | Samsung + |
first launched | 2019 + |
full page name | samsung/microarchitectures/m4 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.2 + |
manufacturer | Samsung + |
microarchitecture type | CPU + |
name | Cheetah + |
pipeline stages | 16 + |
process | 8 nm (0.008 μm, 8.0e-6 mm) + |