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{{phytium title|Xiaomi|arch}} | {{phytium title|Xiaomi|arch}} | ||
{{microarchitecture | {{microarchitecture | ||
− | |atype=CPU | + | | atype = CPU |
− | |name=Xiaomi | + | | name = Xiaomi |
− | |designer=Phytium | + | | designer = Phytium |
− | |manufacturer=TSMC | + | | manufacturer = TSMC |
− | |introduction=2017 | + | | introduction = 2017 |
− | |process=28 nm | + | | phase-out = |
− | |type=Superscalar | + | | process = 28 nm |
− | | | + | | cores = |
− | |speculative=Yes | + | | cores 2 = |
− | |renaming=Yes | + | | cores N = |
− | |isa=ARMv8 | + | |
− | |l1i= | + | | pipeline = Yes |
− | |l1i per= | + | | type = Superscalar |
− | |l1d= | + | | type 2 = |
− | |l1d per= | + | | type N = |
− | |l2= | + | | OoOE = Yes |
− | |l2 per= | + | | speculative = Yes |
− | |l3= | + | | renaming = Yes |
− | |l3 per= | + | | stages = <!-- ONLY IF FIXED SIZE, otherwise use below for range --> |
− | | | + | | stages min = |
− | |core | + | | stages max = |
− | |core name | + | | issues = |
− | | | + | |
− | + | | inst = Yes | |
− | + | | isa = ARMv8 | |
− | + | | feature = | |
− | |core | + | | extension = |
+ | | extension 2 = | ||
+ | | extension N = | ||
+ | |||
+ | | cache = <!-- yes for cache info --> | ||
+ | | l1i = | ||
+ | | l1i per = | ||
+ | | l1i desc = | ||
+ | | l1d = | ||
+ | | l1d per = | ||
+ | | l1d desc = | ||
+ | | l2 = | ||
+ | | l2 per = | ||
+ | | l2 desc = | ||
+ | | l3 = | ||
+ | | l3 per = | ||
+ | | l3 desc = | ||
+ | |||
+ | | core names = Yes | ||
+ | | core name = FTC660 | ||
+ | | core name 2 = FTC661 | ||
+ | | core name N = | ||
}} | }} | ||
'''Xiaomi''' is an [[ARM]] microarchitecture designed in-house by [[Phytium]] for their consumer market and server-based microprocessors. | '''Xiaomi''' is an [[ARM]] microarchitecture designed in-house by [[Phytium]] for their consumer market and server-based microprocessors. | ||
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! Codename !! Brand !! Description | ! Codename !! Brand !! Description | ||
|- | |- | ||
− | | Mars || {{phytium|FT-2000 | + | | Mars || {{phytium|FT-2000}} || |
* High performance | * High performance | ||
* High bandwidth, Large memory | * High bandwidth, Large memory | ||
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* 2x 16-lane [[PCIe]] 3.0 | * 2x 16-lane [[PCIe]] 3.0 | ||
− | === | + | === Panel Architecture === |
− | [[File:xiaomi | + | [[File:xiaomi panel-based data affinity architecture.png|right|450px]] |
+ | Phytium organizes their processors using a grid-layout they call '''Panels''' they call '''Panel-based data affinity architecture'''. Each panel consists of 8 independent [[ARMv8]]-compatible cores. Phytium "Mars" processor consists of 8 such panels for a total of [[64 cores]]. Panels are interconnected with a 2-dimensional mesh network-on-a-chip [[level 2 cache]] with 4 MiB per panel for a total of 32 MiB. | ||
− | + | In addition to the main die, Mars uses an additional '''Cache & Memory chips''' ('''CMC''') auxiliary chips. "Mars" uses 8 such chips connected to the main die providing 16 MiB of [[level 3 cache]] for a total of 128 MiB as well as 8 dual-channel DDR3-1600 [[memory controller]]s for a total maximum bandwidth of 204 GB/s. Mars also provides two 16-lane PCIe 3.0 interfaces. The chips incorporates ECC and parity protection on all caches, tags, and TLBs. | |
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− | === | + | ==== Panel ==== |
− | Each | + | Each Panel consists of 8 cores - each [[ARMv8]]-compatible, supporting AArch32 and AArch64 modes, Exception Levels EL0-EL3, as well as ASIMD-128 operations. Each core has its own inclusive [[L1 cache]] and a shared [[L2 cache]] (4 MiB per panel). Each panel contains two '''Directory Control Units''' ('''DCU''') which are in charge of maintaining directory-based [[cache coherency]] and one routing cell for managing the inter-panel communication. |
− | + | On TSMC's [[28 nm process]], a panel is 6,000 µm x 10,600 µm (63.6 mm²). | |
− | [[ | ||
− | |||
− | + | {| style="border-spacing: 15px;" | |
+ | | [[File:xiaomi panel.png|400px]] || || [[File:xiaomi panel die (28nm).png|300px]] | ||
+ | |} | ||
− | === | + | === Block Diagram === |
− | + | {{empty section}} | |
− | ===== | + | === Memory Hierarchy === |
− | + | {{empty section}} | |
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− | + | === Pipeline === | |
− | + | {{empty section}} | |
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− | {{ | ||
− | == | + | == References == |
− | * | + | * Zhang, C. (2015, August). Mars: A 64-core ARMv8 processor. In ''Hot Chips 27 Symposium'' (HCS), 2015 IEEE (pp. 1-23). IEEE. |
Facts about "Xiaomi - Microarchitectures - Phytium"
codename | Xiaomi + |
designer | Phytium + |
first launched | 2017 + |
full page name | phytium/microarchitectures/xiaomi + |
instance of | microarchitecture + |
instruction set architecture | ARMv8 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Xiaomi + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + |