From WikiChip
Editing nvidia/tegra/xavier
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 31: | Line 31: | ||
== Overview == | == Overview == | ||
[[File:xavier overview.png|right|thumb|Overview (HC 30)]] | [[File:xavier overview.png|right|thumb|Overview (HC 30)]] | ||
− | Xavier is an autonomous machine | + | Xavier is an autonomous machine process designed by [[Nvidia]] and introduced at CES 2018. Silicon came back in the last week of December 2017 with sampling started in the first quarter of 2018. NVIDIA plans on mass production by the end of the year. NVIDIA reported that the product is a result of $2 billion R&D and 8,000 engineering years. The chip is said to have full redundancy and diversity in its functional blocks. |
:[[File:xavier block.svg|500px]] | :[[File:xavier block.svg|500px]] | ||
Line 37: | Line 37: | ||
The design targets and architecture started back in [[2014]]. Fabricated on [[TSMC]] [[12 nm process]], the chip itself comprises an eight-core CPU cluster, GPU with additional inference optimizations, [[neural processor|deep learning accelerator]], vision accelerator, and a set of multimedia accelerators providing additional support for machine learning (stereo, LDC, optical flow). The ISP has been enhanced to provide native HDR support, higher precision math without offloading work to the GPU. Xavier features a large set of I/O and has been designed for safety and reliability supporting various standards such as Functional safety [[ISO-26262]] and [[ASIL]] level C. The CPU cluster is fully [[cache coherent]] and the coherency is extended to all the other [[accelerators]] on-chip. | The design targets and architecture started back in [[2014]]. Fabricated on [[TSMC]] [[12 nm process]], the chip itself comprises an eight-core CPU cluster, GPU with additional inference optimizations, [[neural processor|deep learning accelerator]], vision accelerator, and a set of multimedia accelerators providing additional support for machine learning (stereo, LDC, optical flow). The ISP has been enhanced to provide native HDR support, higher precision math without offloading work to the GPU. Xavier features a large set of I/O and has been designed for safety and reliability supporting various standards such as Functional safety [[ISO-26262]] and [[ASIL]] level C. The CPU cluster is fully [[cache coherent]] and the coherency is extended to all the other [[accelerators]] on-chip. | ||
− | + | One the platform level, one of the bigger changes took place at the I/O subsystem. Xavier features [[NVLink]] 1.0 supporting 20 GB/s in each direction for connecting a [[discrete graphics processor]] to Xavier in a [[cache coherent]] manner. Xavier has PCIe Gen 4.0 support (16 GT/s). It's worth noting that Xavier added support for an end-point mode in addition to the standard root complex support. This support meant they can connect two Xaviers directly one to another (2-way multiprocessing) without going through a PCIe switch or alike. | |
== Architecture == | == Architecture == | ||
Line 48: | Line 48: | ||
[[File:xavier gpu.svg|right|thumb|300px|GPU Block Diagram]] | [[File:xavier gpu.svg|right|thumb|300px|GPU Block Diagram]] | ||
{{main|nvidia/microarchitectures/volta|l1=Volta}} | {{main|nvidia/microarchitectures/volta|l1=Volta}} | ||
− | Xavier implements a derivative of their {{nvidia|Volta|l=arch}} GPU with a set of finer changes to address the machine | + | Xavier implements a derivative of their {{nvidia|Volta|l=arch}} GPU with a set of finer changes to address the machine earning market, paticlarly adding inference performance overtraining. It has eight Volta stream multiprocessors along with their standard 128 KiB of L1 cache and a 512 KiB of shared L2. Compared to Parker, Nvidia claims this GPU has 2.1x the graphics performance. Whereas their desktop parts (e.g., GV100) are a very powerful GPU that is used for training, the GPU here is optimized for inference. The most obvious change is that they added int8 support for lower precision to the CUDA tensor cores and those operate at the full 2x throughput of the FP16 FLOPS. There is also 512 CUDA tensor cores, a number that's comparable to Nvidia's top-end models for machine learning (e.g., the GV100 has 672). All of this yields 22.6 tera-operations (int8) per second. |
{| class="wikitable" | {| class="wikitable" | ||
Line 88: | Line 88: | ||
==== Deep Learning Accelerator ==== | ==== Deep Learning Accelerator ==== | ||
− | The other accelerators on-die is the deep learning accelerator (DLA) which is actually a physical implementation of the open source Nvidia NVDLA architecture. Xavier has two instances of NVDLA which can offer a peak theoretical performance of 5.7 | + | The other accelerators on-die is the deep learning accelerator (DLA) which is actually a physical implementation of the open source Nvidia NVDLA architecture. Xavier has two instances of NVDLA which can offer a peak theoretical performance of 5.7 teraFLOPS (half precision FP) or twice the throughput at 11.4 TOPS for int8. |
{| class="wikitable" | {| class="wikitable" | ||
Line 96: | Line 96: | ||
| 11.4 TOPS (int8) | | 11.4 TOPS (int8) | ||
|- | |- | ||
− | | 5.7 | + | | 5.7 FLOPS (FP16) |
|} | |} | ||
Line 182: | Line 182: | ||
:[[File:xavier die mm-dl accel.png|750px]] | :[[File:xavier die mm-dl accel.png|750px]] | ||
− | == | + | == Borads == |
<gallery mode=packed-hover heights="300px" widths="300px"> | <gallery mode=packed-hover heights="300px" widths="300px"> | ||
jetson_xavier_(front).png|Jetson Xavier, front | jetson_xavier_(front).png|Jetson Xavier, front | ||
Line 190: | Line 190: | ||
== Documents == | == Documents == | ||
* [[:File:ces2018 - nvidia drive xavier.pdf|CES 2018: Nvidia Drive Xavier]] | * [[:File:ces2018 - nvidia drive xavier.pdf|CES 2018: Nvidia Drive Xavier]] | ||
− | |||
− | |||
− | |||
== Bibliography == | == Bibliography == | ||
* IEEE Hot Chips 30 Symposium (HCS) 2018. | * IEEE Hot Chips 30 Symposium (HCS) 2018. | ||
− |
Facts about "Tegra Xavier - Nvidia"
core count | 8 + |
core name | Carmel + |
designer | Nvidia + |
die area | 350 mm² (0.543 in², 3.5 cm², 350,000,000 µm²) + |
family | Tegra + |
first announced | January 8, 2018 + |
first launched | June 2018 + |
full page name | nvidia/tegra/xavier + |
has ecc memory support | true + |
instance of | microprocessor + |
isa | ARMv8 + |
isa family | ARM + |
ldate | June 2018 + |
main image | + |
manufacturer | TSMC + |
market segment | Artificial Intelligence + and Embedded + |
max cpu count | 4 + |
max memory bandwidth | 127.1 GiB/s (130,150.4 MiB/s, 136.473 GB/s, 136,472.586 MB/s, 0.124 TiB/s, 0.136 TB/s) + |
max memory channels | 8 + |
microarchitecture | Carmel + and Volta + |
model number | Tegra194 + |
name | Xavier + |
process | 12 nm (0.012 μm, 1.2e-5 mm) + |
smp max ways | 4 + |
supported memory type | LPDDR4X-4266 + |
tdp | 30 W (30,000 mW, 0.0402 hp, 0.03 kW) + |
tdp (typical) | 20 W (20,000 mW, 0.0268 hp, 0.02 kW) + |
technology | CMOS + |
thread count | 8 + |
transistor count | 9,000,000,000 + |
word size | 64 bit (8 octets, 16 nibbles) + |