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− | {{nvidia title| | + | {{nvidia title|Drive Xavier}} |
{{chip | {{chip | ||
− | |name=Xavier | + | |future=Yes |
− | |image= | + | |name=Drive Xavier |
+ | |no image=No | ||
|designer=Nvidia | |designer=Nvidia | ||
|manufacturer=TSMC | |manufacturer=TSMC | ||
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|market=Artificial Intelligence | |market=Artificial Intelligence | ||
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|first announced=January 8, 2018 | |first announced=January 8, 2018 | ||
− | | | + | |series=Drive |
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|isa=ARMv8 | |isa=ARMv8 | ||
|isa family=ARM | |isa family=ARM | ||
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|process=12 nm | |process=12 nm | ||
|transistors=9,000,000,000 | |transistors=9,000,000,000 | ||
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|core count=8 | |core count=8 | ||
|thread count=8 | |thread count=8 | ||
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|tdp=30 W | |tdp=30 W | ||
|tdp typical=20 W | |tdp typical=20 W | ||
}} | }} | ||
− | ''' | + | '''Drive Xavier''' is a {{arch|64}} [[ARM]] high-performance autonomous machine [[neural processor]] designed by [[Nvidia]] and introduced in [[2018]]. The Drive Xavier is incorporated into Nvidia's Drive Pegasus autonomous computer. |
== Overview == | == Overview == | ||
− | + | The Drive Xavier is an autonomous machine [[system on chip]] designed by [[Nvidia]] and introduced at CES 2018. Silicon came back in the last week of December 2017 with sampling started in the first quarter of 2018. NVIDIA plans on mass production by the end of the year. NVIDIA reported that the product is a result of $2 billion R&D and 8,000 engineering hours. The chip is said to have full redundancy and diversity in its functional blocks. That is, the SoC can continue to operate properly even after a fault is detected. | |
− | Xavier is an autonomous machine | ||
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== Architecture == | == Architecture == | ||
=== CPU === | === CPU === | ||
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{{main|nvidia/microarchitectures/carmel|l1=Carmel core}} | {{main|nvidia/microarchitectures/carmel|l1=Carmel core}} | ||
− | The chip features eight | + | The chip features eight {{nvidia|Carmel|l=arch}} core, Nvidia's own custom {{arch|64}} [[ARM]] cores. Those cores have full ECC and parity as well as dual-execution (unknown if lockstep or something a bit different) allowing all code to execute twice for redundancy reasons. |
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=== GPU === | === GPU === | ||
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{{main|nvidia/microarchitectures/volta|l1=Volta}} | {{main|nvidia/microarchitectures/volta|l1=Volta}} | ||
− | + | The chip incorporates a {{nvidia|Volta|l=arch}} GPU with 512 {{nvidia|CUDA Cores}} capable of operating in 64-bit and 32-bit floating point as well as 8-bit integer. This allows the various [[deep learning]] [[artificial neural networks]] types to run efficiently in the format most suitable for them. This translates to 1.3 CUDA TOPS (32-bit FP) and another 20 Tensor Core TOPS (16-bit FP). | |
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=== Accelerators === | === Accelerators === | ||
− | + | The Drive Xavier incorporates a Programmable Vision Accelerator (PVA) for processing computer vision. It is capable of 1.6 [[TOPS]] and the ability to do [[stereo disparity]] (e.g., processing parallax between two camera to obtain useful information such as depth), optical flow (e.g., direction and speed of vectors), and image processing. Additionally, since the chip is expected to be connected to a network of camera (e.g., side, front, inside), the chip is capable of doing real time [[encoding]] for all camera in [[high dynamic range]]. | |
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− | Xavier incorporates a Programmable Vision Accelerator (PVA) for processing computer vision. | ||
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{| class="wikitable" | {| class="wikitable" | ||
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==== Deep Learning Accelerator ==== | ==== Deep Learning Accelerator ==== | ||
− | The | + | The chip incorporates a deep learning accelerator (DLA) that implements a number of specific set of deep learning functions common to many applications. This allows them to read the highest possible energy efficiency for those operations. The DLA has a peak performance of 5 [[TOPS]] for 16-bit integers or 10 [[TOPS]] for 8-bit integer. |
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== Memory controller == | == Memory controller == | ||
{{memory controller | {{memory controller | ||
− | |type= | + | |type=LPDDR4-2133 |
|ecc=Yes | |ecc=Yes | ||
+ | |width=32 bit | ||
|channels=8 | |channels=8 | ||
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|max bandwidth=127.1 GiB/s | |max bandwidth=127.1 GiB/s | ||
}} | }} | ||
== I/O == | == I/O == | ||
− | * [[ | + | * 16 [[Camera Serial Interface|CSI]] channels |
− | + | ** 109 Gbps total bandwidth | |
− | + | * 1x gE interface | |
− | + | * 1x 10gE interface | |
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− | ** 109 Gbps | ||
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== Die == | == Die == | ||
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* 9,000,000,000 transistors | * 9,000,000,000 transistors | ||
* 350 mm² die size | * 350 mm² die size | ||
* [[TSMC]]'s [[12FFN]] | * [[TSMC]]'s [[12FFN]] | ||
− | [[File:nvidia xavier die shot.png|900px]] | + | [[File:nvidia drive xavier die shot.png|900px]] |
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− | + | [[File:nvidia drive xavier die shot (annotated).png|900px]] | |
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== Documents == | == Documents == | ||
* [[:File:ces2018 - nvidia drive xavier.pdf|CES 2018: Nvidia Drive Xavier]] | * [[:File:ces2018 - nvidia drive xavier.pdf|CES 2018: Nvidia Drive Xavier]] | ||
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Facts about "Tegra Xavier - Nvidia"
core count | 8 + |
core name | Carmel + |
designer | Nvidia + |
die area | 350 mm² (0.543 in², 3.5 cm², 350,000,000 µm²) + |
family | Tegra + |
first announced | January 8, 2018 + |
first launched | June 2018 + |
full page name | nvidia/tegra/xavier + |
has ecc memory support | true + |
instance of | microprocessor + |
isa | ARMv8 + |
isa family | ARM + |
ldate | June 2018 + |
main image | + |
manufacturer | TSMC + |
market segment | Artificial Intelligence + and Embedded + |
max cpu count | 4 + |
max memory bandwidth | 127.1 GiB/s (130,150.4 MiB/s, 136.473 GB/s, 136,472.586 MB/s, 0.124 TiB/s, 0.136 TB/s) + |
max memory channels | 8 + |
microarchitecture | Carmel + and Volta + |
model number | Tegra194 + |
name | Xavier + |
process | 12 nm (0.012 μm, 1.2e-5 mm) + |
smp max ways | 4 + |
supported memory type | LPDDR4X-4266 + |
tdp | 30 W (30,000 mW, 0.0402 hp, 0.03 kW) + |
tdp (typical) | 20 W (20,000 mW, 0.0268 hp, 0.02 kW) + |
technology | CMOS + |
thread count | 8 + |
transistor count | 9,000,000,000 + |
word size | 64 bit (8 octets, 16 nibbles) + |