Editing nervana/nnp/nnp-i 1300

{{nervana title|NNP-I 1300}}
{{chip
|name=NNP-I 1300
|image=spring_hill_package_(front).png
|back image=spring_hill_package_(back).png
|designer=Intel
|manufacturer=Intel
|model number=NNP-I 1300
|market=Server
|market 2=Edge
|first announced=November 12, 2019
|first launched=November 12, 2019
|family=NNP
|series=NNP-I
|microarch=Spring Hill
|microarch 2=Sunny Cove
|process=10 nm
|transistors=8,500,000,000
|technology=CMOS
|die area=239 mm²
|core count=24
|tdp=75 W
}}
'''NNP-I 1300''' is an inference [[neural processor]] designed by [[Intel Nervana]] and introduced in late 2019. Fabricated on [[Intel's 10 nm process]] based on the {{intel|Spring Hill|l=arch}} microarchitecture, the NNP-I 1300 comes in a PCIe Gen 3.0 [[accelerator card]] form factor with two NPU chips, each with all 24 {{intel|Spring Hill#Inference Compute Engine (ICE)|ICEs|l=arch}} enabled for a peak performance of 170 [[TOPS]] at a TDP of 75 W.

== Peak Performance ==
The NNP-I 1300 has a peak performance of [[peak integer ops (8-bit)::170 TOPS]] ([[Int8]]).

== Cache ==
{{main|intel/microarchitectures/spring_hill#Memory_Hierarchy|l1=Spring Hill § Cache}}
* 3 MiB of tightly-coupled scratchpad memory
** 12 x 256 KiB/core
* 48 MiB Deep SRAM
** 4 MiB/ICE
* 24 MiB [[last level cache|LLC]]
** 3 MiB/slice

== Memory controller ==
{{memory controller
|type=LPDDR4X-4200
|ecc=Yes
|max mem=32 GiB
|controllers=4
|width=16
|max bandwidth=67.2 GB/s
}}

== Die ==
{{main|intel/microarchitectures/spring_hill#Die|l1=Spring Hill § Die}}
* 8,500,000,000 transistors
* 239 mm² die size

== Product Brief ==
* [[:File:16433-1 NNP-announce NNP-I brief v5.1.pdf|Intel NNP-I Product Brief]]
back image	+
core count	24 +
designer	Intel +
die area	239 mm² (0.37 in², 2.39 cm², 239,000,000 µm²) +
family	NNP +
first announced	November 12, 2019 +
first launched	November 12, 2019 +
full page name	nervana/nnp/nnp-i 1300 +
has ecc memory support	true +
instance of	microprocessor +
ldate	November 12, 2019 +
main image	+
manufacturer	Intel +
market segment	Server + and Edge +
max memory bandwidth	62.585 GiB/s (64,086.914 MiB/s, 67.2 GB/s, 67,200 MB/s, 0.0611 TiB/s, 0.0672 TB/s) +
microarchitecture	Spring Hill + and Sunny Cove +
model number	NNP-I 1300 +
name	NNP-I 1300 +
peak integer ops (8-bit)	170,000,000,000,000 OPS (170,000,000,000 KOPS, 170,000,000 MOPS, 170,000 GOPS, 170 TOPS, 0.17 POPS, 1.7e-4 EOPS, 1.7e-7 ZOPS) +
process	10 nm (0.01 μm, 1.0e-5 mm) +
series	NNP-I +
supported memory type	LPDDR4X-4200 +
tdp	75 W (75,000 mW, 0.101 hp, 0.075 kW) +
technology	CMOS +
transistor count	8,500,000,000 +