From WikiChip
Editing movidius/microarchitectures/shave v2.0
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 8: | Line 8: | ||
|phase-out=2014 | |phase-out=2014 | ||
|process=65 nm | |process=65 nm | ||
− | |type= | + | |type=VLIW |
|isa=SHAVE | |isa=SHAVE | ||
|isa 2=SPARC v8 | |isa 2=SPARC v8 | ||
Line 26: | Line 26: | ||
== History == | == History == | ||
− | The original SHAVE architecture was designed primarily for the [[hardware acceleration|acceleration]] of game physics. Low demand for expensive physics acceleration in smartphones has forced | + | The original SHAVE architecture was designed primarily for the [[hardware acceleration|acceleration]] of game physics. Low demand for expensive physics acceleration in smartphones has forced to re-focused on image and vision processing. Their architecture was versatile enough that it allowed for fairly simple modification to target machine vision processing. |
== Process Technology == | == Process Technology == | ||
Line 91: | Line 91: | ||
=== Execution Units === | === Execution Units === | ||
[[File:shave v2 eus.png|right|400px]] | [[File:shave v2 eus.png|right|400px]] | ||
− | The three major arithmetic execution units are the vector arithmetic unit (VAU), the scalar arithmetic unit (SAU), and the integer arithmetic unit (IAU) | + | The three major arithmetic execution units are the vector arithmetic unit (VAU), the scalar arithmetic unit (SAU), and the integer arithmetic unit (IAU). |
− | The '''integer arithmetic unit''' ('''IAU''') performs all arithmetic instructions that operate on 32-bit integer numbers and access the IRF. The '''scalar arithmetic unit''' ('''SAU''') is far more versatile and can perform all [[integer]] (8-32 bit) and [[floating point]] (HP/FP) operations. The '''vector arithmetic unit''' ('''VAU''') supports 128-bit vector operations of all the integer (8-32 bit) and floating point (HP/FP) types | + | The '''integer arithmetic unit''' ('''IAU''') performs all arithmetic instructions that operate on 32-bit integer numbers and access the IRF. The '''scalar arithmetic unit''' ('''SAU''') is far more versatile and can perform all [[integer]] (8-32 bit) and [[floating point]] (HP/FP) operations. The '''vector arithmetic unit''' ('''VAU''') supports 128-bit vector operations of all the integer (8-32 bit) and floating point (HP/FP) types. |
− | In addition to those units, there is also a '''compare-move unit''' ( | + | In addition to those units, there is also a '''compare-move unit''' (CMU) which is used to generate [[predicates]]. This unit can do things such as three comparison operations per 16-bit/32-bit/8bit entry in the vector register file in parallel with the vector operations which can generate predicates for predicated execution. The CMU effectively interfaces with all the register files and is capable of moving data between them. |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
=== Bandwidth === | === Bandwidth === | ||
Line 142: | Line 130: | ||
:[[File:movidius shave v2.0 sparse data support.png|700px]] | :[[File:movidius shave v2.0 sparse data support.png|700px]] | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
== Performance claims == | == Performance claims == | ||
Line 157: | Line 138: | ||
== Package == | == Package == | ||
[[File:myriad 1 bga.png|right|200px]] | [[File:myriad 1 bga.png|right|200px]] | ||
− | Movidius packaged those chips in an 8x8 mm [[BGA]] package with 225 [[solder ball|balls]]. The die is then | + | Movidius packaged those chips in an 8x8 mm [[BGA]] package with 225 [[solder ball|balls]]. The die is then bumpped on top of a custom [[FR-4 substrate]]. The SDRAM is then [[wire bond|wire bond]] on top of the Myriad die. |
:[[File:myriad package diagram.svg|600px]] | :[[File:myriad package diagram.svg|600px]] | ||
Line 171: | Line 152: | ||
− | :[[File:myriad 1 (shave v2.0) die shot.png | + | :[[File:myriad 1 (shave v2.0) die shot.png|600px]] |
:[[File:myriad 1 (shave v2.0) die shot (annotated).png|600px]] | :[[File:myriad 1 (shave v2.0) die shot (annotated).png|600px]] | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
== References == | == References == | ||
* Some information was obtained directly from Movidius | * Some information was obtained directly from Movidius | ||
* HotChips 23 (HC23), 2011 | * HotChips 23 (HC23), 2011 |
Facts about "SHAVE v2.0 - Microarchitectures - Intel Movidius"
codename | SHAVE v2.0 + |
designer | Movidius + |
first launched | 2011 + |
full page name | movidius/microarchitectures/shave v2.0 + |
instance of | microarchitecture + |
instruction set architecture | SHAVE + and SPARC v8 + |
manufacturer | TSMC + |
name | SHAVE v2.0 + |
phase-out | 2014 + |
process | 65 nm (0.065 μm, 6.5e-5 mm) + |