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{{mips title|Coprocessor 0}} | {{mips title|Coprocessor 0}} | ||
− | '''Coprocessor 0''' (also known as the '''CP0''' or '''system control coprocessor''') is a required | + | '''Coprocessor 0''' (also known as the '''CP0''' or '''system control coprocessor''') is a required coprocessor part of the {{mips|MIPS32}} and {{mips|MIPS64}} ISA which provides the facilities needed for an operating system. |
== Coprocessor 0 instructions == | == Coprocessor 0 instructions == | ||
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{| class="wikitable sortable" | {| class="wikitable sortable" | ||
− | ! | + | ! Regsiter Mnemonic || Register Number || Description |
|- | |- | ||
| [[Index register - MIPS|Context]] || 0 || rowspan="8" | memory management (TLB) | | [[Index register - MIPS|Context]] || 0 || rowspan="8" | memory management (TLB) |