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− | '''Intel Corporation''' is an American [[semiconductor]] company. While most notably known for their development of [[microprocessors]] and [[x86]], Intel also designs and manufactures other [[integrated circuit]]s including [[flash memory]], [[network interface controller]]s, [[GPU]]s, [[chipset]]s, motherboards, and computers. | + | '''Intel Corporation''' is a [[semiconductor]] [[integrated circuit|chip]] maker. |
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− | In addition to [[x86]], Intel used to also design and manufacture [[ARM]]-based chips as well as embed [[ARC]]-based cores in their products. While they no longer sell such chips, they still use ARM processors in various products (e.g. in their FPGAs) as well as still retain full a architectural level ARM license allowing them to design and sell their own ARM devices should they wish to.
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− | == Subsidiaries ==
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− | * [[Barefoot Networks]]
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− | * [[Movidius]]
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− | * [[Nervana]]
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− | * [[Mobileye]]
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| | | |
| == Find Chip == | | == Find Chip == |
| * By {{intel|S-Spec}} | | * By {{intel|S-Spec}} |
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− | == List of processor families == | + | == Processor Families == |
| {{collist | | {{collist |
| | count = 4 | | | count = 4 |
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| * {{intel|Core i3}} | | * {{intel|Core i3}} |
| * {{intel|Core i5}} | | * {{intel|Core i5}} |
− | * {{intel|Core i7}} | + | * {{intel|Core i7|Core i7}} |
| * {{intel|Core i7 EE}} | | * {{intel|Core i7 EE}} |
− | * {{intel|Core i9}}
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| * {{intel|Core M}} | | * {{intel|Core M}} |
| * {{intel|Core Solo}} | | * {{intel|Core Solo}} |
− | * {{intel|EP80579}}
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| * {{intel|i860}} | | * {{intel|i860}} |
| * {{intel|i960}} | | * {{intel|i960}} |
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| * {{intel|Mobile Pentium II}} | | * {{intel|Mobile Pentium II}} |
| * {{intel|Pentium}} | | * {{intel|Pentium}} |
− | * {{intel|Pentium (2009)}}
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| * {{intel|Pentium 4}} | | * {{intel|Pentium 4}} |
| * {{intel|Pentium 4 EE}} | | * {{intel|Pentium 4 EE}} |
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| * {{intel|Pentium D}} | | * {{intel|Pentium D}} |
| * {{intel|Pentium EE}} | | * {{intel|Pentium EE}} |
− | * {{intel|Pentium Gold}}
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| * {{intel|Pentium II}} | | * {{intel|Pentium II}} |
| * {{intel|Pentium III}} | | * {{intel|Pentium III}} |
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| * {{intel|Pentium MMX}} | | * {{intel|Pentium MMX}} |
| * {{intel|Pentium Pro}} | | * {{intel|Pentium Pro}} |
− | * {{intel|Pentium Silver}}
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− | * {{intel|PXA}}
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| * {{intel|Quark}} | | * {{intel|Quark}} |
| * {{intel|Xeon}} | | * {{intel|Xeon}} |
− | * {{intel|Xeon Bronze}}
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| * {{intel|Xeon D}} | | * {{intel|Xeon D}} |
− | * {{intel|Xeon E}}
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| * {{intel|Xeon E3}} | | * {{intel|Xeon E3}} |
| * {{intel|Xeon E5}} | | * {{intel|Xeon E5}} |
| * {{intel|Xeon E7}} | | * {{intel|Xeon E7}} |
− | * {{intel|Xeon Gold}}
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− | * {{intel|Xeon Platinum}}
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− | * {{intel|Xeon Silver}}
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− | * {{intel|Xeon W}}
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| }} | | }} |
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− | == List of architectures == | + | == Instruction set architectures == |
| {{collist | | {{collist |
| | count = 1 | | | count = 1 |
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− | * {{\\|MCS-8/ISA|MCS-8 (8008)}} | + | * {{intel|MCS-8/ISA|MCS-8 (8008)}} |
− | * [[x86]]
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− | * {{\\|Configurable Spatial Accelerator}} (CSA)
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− | * {{\\|Programmable Unified Memory Architecture}} (PUMA)
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| }} | | }} |
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− | == List of microarchitectures == | + | == Microarchitectures == |
− | '''Mainstream ([[x86]]):''' | + | '''Mainstream:''' |
| {{collist | | {{collist |
| | count = 4 | | | count = 4 |
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− | * {{intel|80186|l=arch}} | + | * {{intel|80186}} |
− | * {{intel|80286|l=arch}} | + | * {{intel|80286}} |
− | * {{intel|80386|l=arch}} | + | * {{intel|80386}} |
− | * {{intel|80486|l=arch}} | + | * {{intel|80486}} |
− | * {{intel|P5|l=arch}} | + | * {{intel|P5}} |
− | * {{intel|P6|l=arch}} | + | * {{intel|P6}} |
− | * {{intel|NetBurst|l=arch}} | + | * {{intel|NetBurst}} |
− | * {{intel|Enhanced NetBurst|l=arch}} | + | * {{intel|microarchitectures/Core|Core}} |
− | }}
| + | * {{intel|Penryn}} |
− | | + | * {{intel|Nehalem}} |
− | | + | * {{intel|Westmere}} |
− | {{collist
| + | * {{intel|Sandy Bridge}} |
− | | count = 4
| + | * {{intel|Ivy Bridge}} |
− | | style= margin-left: 20px;
| + | * {{intel|Haswell}} |
− | |
| + | * {{intel|Broadwell}} |
− | '''Client SoC:'''
| + | * {{intel|Skylake}} |
− | * {{intel|Core (client)|l=arch}}
| + | * {{intel|Kaby Lake}} |
− | * {{intel|Penryn (client)|l=arch}} | + | * {{intel|Coffee Lake}} |
− | * {{intel|Nehalem (client)|l=arch}} | + | * {{intel|Cannonlake}} |
− | * {{intel|Westmere (client)|l=arch}} | + | * {{intel|Icelake}} |
− | * {{intel|Sandy Bridge (client)|l=arch}} | + | * {{intel|Tigerlake}} |
− | * {{intel|Ivy Bridge (client)|l=arch}} | |
− | * {{intel|Haswell (client)|l=arch}} | |
− | * {{intel|Broadwell (client)|l=arch}} | |
− | * {{intel|Skylake (client)|l=arch}} | |
− | * {{intel|Kaby Lake|l=arch}} | |
− | * {{intel|Coffee Lake|l=arch}} | |
− | * {{intel|Whiskey Lake|l=arch}}
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− | * {{intel|Amber Lake|l=arch}}
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− | * {{intel|Comet Lake|l=arch}}
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− | * {{intel|Keystone Lake|l=arch}}
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− | * {{intel|Rocket Lake|l=arch}}
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− | * {{intel|Cannon Lake|l=arch}} ("Skymont")
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− | * {{intel|Ice Lake (client)|l=arch}}
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− | * {{intel|Tiger Lake|l=arch}}
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− | * {{intel|Alder Lake|l=arch}}
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− | * {{intel|Raptor Lake|l=arch}}
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− | * {{intel|Meteor Lake|l=arch}}
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− | * {{intel|Arrow Lake|l=arch}}
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− | * {{intel|Lunar Lake|l=arch}}
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− | | |
− | }}
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− | | |
− | | |
− | {{collist
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− | | count = 4
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− | | style= margin-left: 20px;
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− | |
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− | '''Server SoC:'''
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− | * {{intel|Core (server)|l=arch}}
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− | * {{intel|Penryn (server)|l=arch}}
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− | * {{intel|Nehalem (server)|l=arch}}
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− | * {{intel|Westmere (server)|l=arch}}
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− | * {{intel|Sandy Bridge (server)|l=arch}}
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− | * {{intel|Ivy Bridge (server)|l=arch}}
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− | * {{intel|Haswell (server)|l=arch}}
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− | * {{intel|Broadwell (server)|l=arch}}
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− | * {{intel|Skylake (server)|l=arch}}
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− | * {{intel|Cascade Lake|l=arch}}
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− | * {{intel|Cooper Lake|l=arch}}
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− | * {{intel|Ice Lake (server)|l=arch}}
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− | * {{intel|Sapphire Rapids|l=arch}}
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− | * {{intel|Emerald Rapids|l=arch}}
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− | * {{intel|Granite Rapids|l=arch}}
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− | * {{intel|Diamond Rapids|l=arch}}
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− | }}
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− | | |
− | {{collist
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− | | count = 4
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− | | style= margin-left: 20px;
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− | |
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− | '''Networking SoC:'''
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− | * {{intel|Snow Ridge|l=arch}}
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− | * {{intel|Tanner Ridge|l=arch}}
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− | }}
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− | | |
− | | |
− | {{collist
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− | | count = 4
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− | | style= margin-left: 20px;
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− | |
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− | '''High-Perf (Big Cores):'''
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− | * {{intel|Palm Cove|l=arch}}
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− | * {{intel|Sunny Cove|l=arch}} | |
− | * {{intel|Willow Cove|l=arch}} | |
− | * {{intel|Golden Cove|l=arch}} | |
− | * {{intel|Ocean Cove|l=arch}}
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| }} | | }} |
− | | + | '''ULP:''' |
− | | |
− | {{collist
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− | | count = 4
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− | | style= margin-left: 20px;
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− | '''High-Efficiency (Small Cores)'''
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− | * {{intel|Bonnell|l=arch}}
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− | * {{intel|Saltwell|l=arch}}
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− | * {{intel|Silvermont|l=arch}}
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− | * {{intel|Airmont|l=arch}}
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− | * {{intel|Goldmont|l=arch}}
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− | * {{intel|Goldmont Plus|l=arch}}
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− | * {{intel|Tremont|l=arch}}
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− | }}
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− | | |
− | '''MCU:'''
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− | {{collist
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− | | count = 1
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− | * {{intel|Lakemont|l=arch}}
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− | }}
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− | | |
− | '''ULP ([[ARM]]):''' | |
− | {{collist
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− | | count = 3
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− | |
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− | * .. From [[DEC]]
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− | * {{intel|XScale|l=arch}}
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− | * {{intel|XScale 2|l=arch}}
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− | * {{intel|XScale 3|l=arch}}
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− | * {{intel|Mohawk|l=arch}}
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− | * Continued by [[Marvell]] ..
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− | }}
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− | '''Server (EPIC) ([[Itanium]]):'''
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− | {{collist
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− | | count = 4
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− | |
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− | * {{intel|Merced|l=arch}}
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− | * {{intel|McKinley|l=arch}}
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− | * {{intel|Madison|l=arch}}
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− | * {{intel|Deerfield|l=arch}}
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− | * {{intel|Hondo|l=arch}}
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− | * {{intel|Madison 9M|l=arch}}
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− | * {{intel|Fanwood|l=arch}}
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− | * {{intel|Montecito|l=arch}}
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− | * {{intel|Chivano|l=arch}}
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− | * {{intel|Millington|l=arch}}
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− | * {{intel|Montvale|l=arch}}
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− | * {{intel|Tukwila|l=arch}}
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− | * {{intel|Dimona|l=arch}}
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− | * {{intel|Poulson|l=arch}}
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− | * {{intel|Kittson|l=arch}}
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− | }}
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− | '''[[Many-core]]:'''
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| {{collist | | {{collist |
| | count = 2 | | | count = 2 |
− | | style= margin-left: 20px; | + | | width = 300px |
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− | '''Early Research:'''
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− | * {{intel|Polaris|l=arch}}
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− | * {{intel|Larrabee|l=arch}}
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− | * {{intel|Rock Creek|l=arch}}
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− | }}
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− | {{clear}}
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− | {{collist
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− | | count = 3
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− | | style= margin-left: 20px;
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− | '''{{intel|MIC Architectures}}:'''
| + | * {{intel|Bonnell}} |
− | * {{intel|Knights Ferry|l=arch}} (Aubrey Isle)
| + | * {{intel|Saltwell}} |
− | * {{intel|Knights Corner|l=arch}} (Angel Isle)
| + | * {{intel|Silvermont}} |
− | * {{intel|Knights Landing|l=arch}}
| + | * {{intel|Airmont}} |
− | * {{intel|Knights Mill|l=arch}}
| + | * {{intel|Goldmont}} |
− | * {{intel|Knights Hill|l=arch}}
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− | * {{intel|Knights Peak|l=arch}}
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− | }}
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− | '''Heterogeneous:'''
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− | {{collist
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− | | count = 1
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− | * {{intel|Lakefield|l=arch}}
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− | * {{intel|Ryefield|l=arch}}
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− | }}
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− | | |
− | | |
− | '''GPU:'''
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− | {{collist
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− | | count = 3
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− | | style= margin-left: 20px;
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− | |
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− | '''Integrated:'''
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− | * {{intel|Gen1|l=arch}}
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− | * {{intel|Gen2|l=arch}}
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− | * {{intel|Gen3|l=arch}}
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− | * {{intel|Gen3.5|l=arch}}
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− | * {{intel|Gen4|l=arch}}
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− | * {{intel|Gen5|l=arch}}
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− | * {{intel|Gen5.75|l=arch}} ("Ironlake")
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− | * {{intel|Gen6|l=arch}} | |
− | * {{intel|Gen7|l=arch}} | |
− | * {{intel|Gen7.5|l=arch}} | |
− | * {{intel|Gen8|l=arch}} | |
− | * {{intel|Gen9|l=arch}} | |
− | * {{intel|Gen9.5|l=arch}}
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− | * {{intel|Gen10|l=arch}}
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− | * {{intel|Gen11|l=arch}}
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− | * {{intel|Gen12|l=arch}}
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− | }}
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− | {{clear}}
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− | {{collist
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− | | count = 1
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− | | style= margin-left: 20px;
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− | |
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− | '''Discrete:'''
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− | * {{intel|Arctic Sound|l=arch}}
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− | * {{intel|Jupiter Sound|l=arch}}
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− | }}
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− | | |
− | '''Artificial Intelligence:'''
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− | {{collist
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− | | count = 3
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− | | style= margin-left: 20px;
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− | '''Training:'''
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− | * {{intel|Lake Crest|l=arch}}
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− | * {{intel|Spring Crest|l=arch}}
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− | }}
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− | {{clear}}
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− | {{collist
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− | | count = 3
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− | | style= margin-left: 20px;
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− | |
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− | '''Inference:'''
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− | * {{intel|Spring Hill|l=arch}}
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| }} | | }} |
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| | count = 1 | | | count = 1 |
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− | '''Neuromorphic:'''
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− | * {{intel|Loihi}}
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− | * {{intel|Loihi 2}}
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− | '''Artificial Intelligence'''
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− | * {{intel|ETANN}}
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− | '''Quantum:'''
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− | * {{intel|Surface-17}}
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− | * {{intel|Tangle Lake}}
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− | '''RAM:'''
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| * {{intel|3101}} | | * {{intel|3101}} |
| * {{intel|1103}} | | * {{intel|1103}} |
− | }}
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− |
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− | == Architectural Concepts ==
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− | {{collist
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− | | count = 1
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− | * {{\\|Mesh Interconnect Architecture}}
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− | * {{\\|Ring Interconnect Architecture}}
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| }} | | }} |
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| {{collist | | {{collist |
| | count = 2 | | | count = 2 |
| + | | width = 500px |
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− | * {{\\|CPUID}} | + | * {{intel|Tick-Tock}} |
− | * {{\\|CNVi}}
| + | * {{intel|Process-Architecture-Optimization}} |
− | * {{\\|Flexpoint}}
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− | * {{\\|Frequency Behavior}}
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− | * {{\\|Innovation Engine}} (IE) | |
− | * {{\\|Management Engine}} (ME)
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− | * {{\\|Process-Architecture-Optimization}} (PAO)
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− | * {{\\|Process Technology}}
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− | * {{\\|Tick-Tock}}
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− | }}
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− | | |
− | == Technologies ==
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− | {{collist
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− | | count = 2
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− | * {{\\|Dynamic Tuning}}
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− | * {{\\|Hyper Scaling}}
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− | * {{\\|Speed Select Technology}} (SST)
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− | * {{\\|Turbo Boost Technology}} (TBT)
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− | * {{\\|Thermal Velocity Boost}} (TVB)
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− | * {{\\|DL Boost}}
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| }} | | }} |
− |
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− | == Packaging Technologies ==
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− | {{collist
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− | | count = 2
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− | |
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− | * {{\\|Foveros}}
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− | * {{\\|EMIB}}
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− | }}
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− |
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− | == Documents ==
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− | See {{\\|Documents}}.
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| [[Category:intel]] | | [[Category:intel]] |