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{{intel title|Xeon W-3223}} | {{intel title|Xeon W-3223}} | ||
{{chip | {{chip | ||
+ | |future=Yes | ||
|name=Xeon W-3223 | |name=Xeon W-3223 | ||
− | |image= | + | |no image=Yes |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|model number=W-3223 | |model number=W-3223 | ||
|part number=CD8069504248402 | |part number=CD8069504248402 | ||
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|market=Workstation | |market=Workstation | ||
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|family=Xeon W | |family=Xeon W | ||
|series=W-3200 | |series=W-3200 | ||
|locked=Yes | |locked=Yes | ||
|frequency=3,500 MHz | |frequency=3,500 MHz | ||
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|clock multiplier=35 | |clock multiplier=35 | ||
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
|microarch=Cascade Lake | |microarch=Cascade Lake | ||
− | |core name=Cascade Lake | + | |core name=Cascade Lake W |
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|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
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|thread count=16 | |thread count=16 | ||
|max cpus=1 | |max cpus=1 | ||
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|tdp=160 W | |tdp=160 W | ||
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}} | }} | ||
− | '''W-3223''' is a {{arch|64}} [[octa-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2019]]. This | + | '''W-3223''' is a {{arch|64}} [[octa-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2019]]. This processors, which is fabricated on an enhanced [[14 nm process|14nm++ process]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture, operates at 3.5 GHz with a [[TDP]] of 160 W and a {{intel|turbo boost}} frequency of up to ? GHz. |
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+ | {{unknown features}} | ||
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== Cache == | == Cache == | ||
− | {{main|intel/microarchitectures/ | + | {{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}} |
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{{cache size | {{cache size | ||
|l1 cache=512 KiB | |l1 cache=512 KiB | ||
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|l2 desc=16-way set associative | |l2 desc=16-way set associative | ||
|l2 policy=write-back | |l2 policy=write-back | ||
− | |l3 cache= | + | |l3 cache=11 MiB |
− | |l3 break= | + | |l3 break=8x1.375 MiB |
|l3 desc=11-way set associative | |l3 desc=11-way set associative | ||
|l3 policy=write-back | |l3 policy=write-back | ||
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== Memory controller == | == Memory controller == | ||
{{memory controller | {{memory controller | ||
− | |type=DDR4- | + | |type=DDR4-2933 |
|ecc=Yes | |ecc=Yes | ||
− | |max mem=1 TiB | + | |max mem=1.5 TiB |
|controllers=2 | |controllers=2 | ||
|channels=6 | |channels=6 | ||
− | |max bandwidth= | + | |max bandwidth=131.13 GiB/s |
− | |bandwidth schan= | + | |bandwidth schan=21.86 GiB/s |
− | |bandwidth dchan= | + | |bandwidth dchan=43.71 GiB/s |
− | |bandwidth qchan= | + | |bandwidth qchan=87.42 GiB/s |
− | |bandwidth hchan= | + | |bandwidth hchan=131.13 GiB/s |
}} | }} | ||
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|type=PCIe | |type=PCIe | ||
|pcie revision=3.0 | |pcie revision=3.0 | ||
− | |pcie lanes= | + | |pcie lanes=48 |
|pcie config=x16 | |pcie config=x16 | ||
|pcie config 2=x8 | |pcie config 2=x8 | ||
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|avx512vbmi=No | |avx512vbmi=No | ||
|avx5124fmaps=No | |avx5124fmaps=No | ||
− | |||
|avx5124vnniw=No | |avx5124vnniw=No | ||
|avx512vpopcntdq=No | |avx512vpopcntdq=No | ||
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|clmul=Yes | |clmul=Yes | ||
|f16c=Yes | |f16c=Yes | ||
− | |||
|tbt1=No | |tbt1=No | ||
|tbt2=Yes | |tbt2=Yes | ||
− | |tbmt3 | + | |tbmt3=No |
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|bpt=No | |bpt=No | ||
|eist=Yes | |eist=Yes | ||
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|osguard=Yes | |osguard=Yes | ||
|intqat=No | |intqat=No | ||
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|3dnow=No | |3dnow=No | ||
|e3dnow=No | |e3dnow=No | ||
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|sensemi=No | |sensemi=No | ||
|xfr=No | |xfr=No | ||
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}} | }} |
Facts about "Xeon W-3223 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon W-3223 - Intel#pcie + |
base frequency | 3,500 MHz (3.5 GHz, 3,500,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
clock multiplier | 35 + |
core count | 8 + |
core name | Cascade Lake SP + |
core stepping | B1 + |
designer | Intel + |
family | Xeon W + |
first announced | June 3, 2019 + |
first launched | June 3, 2019 + |
full page name | intel/xeon w/w-3223 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Secure Key Technology +, OS Guard +, Identity Protection Technology +, Turbo Boost Max Technology 3.0 + and Deep Learning Boost + |
has intel deep learning boost | true + |
has intel enhanced speedstep technology | true + |
has intel identity protection technology support | true + |
has intel secure key technology | true + |
has intel speed shift technology | true + |
has intel supervisor mode execution protection | true + |
has intel trusted execution technology | true + |
has intel turbo boost max technology 3 0 | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
intel turbo boost max technology 3 0 frequency | 4,200 MHz (4.2 GHz, 4,200,000 kHz) + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) + |
ldate | June 3, 2019 + |
main image | + |
manufacturer | Intel + |
market segment | Workstation + |
max cpu count | 1 + |
max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
max memory channels | 6 + |
microarchitecture | Cascade Lake + |
model number | W-3223 + |
name | Xeon W-3223 + |
number of avx-512 execution units | 2 + |
package | FCLGA-3647 + |
part number | CD8069504248402 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 749.00 (€ 674.10, £ 606.69, ¥ 77,394.17) + |
release price (tray) | $ 749.00 (€ 674.10, £ 606.69, ¥ 77,394.17) + |
s-spec | SRFFG + |
series | W-3200 + |
smp max ways | 1 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2666 + |
tdp | 160 W (160,000 mW, 0.215 hp, 0.16 kW) + |
technology | CMOS + |
thread count | 16 + |
turbo frequency (1 core) | 4,000 MHz (4 GHz, 4,000,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |
x86/has memory protection extensions | true + |