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{{intel title|Xeon Gold 6254}} | {{intel title|Xeon Gold 6254}} | ||
{{chip | {{chip | ||
+ | |future=Yes | ||
|name=Xeon Gold 6254 | |name=Xeon Gold 6254 | ||
− | |image= | + | |image=skylake sp (basic).png |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|model number=6254 | |model number=6254 | ||
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|market=Server | |market=Server | ||
− | |first announced= | + | |first announced=December, 2018 |
− | |first launched= | + | |first launched=December, 2018 |
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|family=Xeon Gold | |family=Xeon Gold | ||
− | |series= | + | |series=6000 |
|locked=Yes | |locked=Yes | ||
|frequency=3,100 MHz | |frequency=3,100 MHz | ||
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|bus rate=8 GT/s | |bus rate=8 GT/s | ||
|clock multiplier=31 | |clock multiplier=31 | ||
+ | |cpuid=0x50655 | ||
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
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|core name=Cascade Lake SP | |core name=Cascade Lake SP | ||
|core family=6 | |core family=6 | ||
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|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
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|core count=18 | |core count=18 | ||
|thread count=36 | |thread count=36 | ||
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|max cpus=4 | |max cpus=4 | ||
− | + | |package module 1={{packages/intel/fclga-3647}} | |
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}} | }} | ||
− | '''Xeon Gold 6254''' is a {{arch|64}} [[18-core]] [[x86]] high performance server microprocessor | + | '''Xeon Gold 6254''' is a {{arch|64}} [[18-core]] [[x86]] multi-socket high performance server microprocessor that was supposed to be released in December of 2018, and has yet to be released because Intel sucks donkey nuts. This chip supports up to 4-way multiprocessing. The Gold 6254, which is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm++ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 3.1 GHz with a TDP of ? W and a {{intel|turbo boost}} frequency of up to 4 GHz, supports up ? GiB of hexa-channel DDR4-2666 ECC memory. |
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+ | {{unknown features}} | ||
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== Memory controller == | == Memory controller == | ||
{{memory controller | {{memory controller | ||
− | |type=DDR4- | + | |type=DDR4-2666 |
|ecc=Yes | |ecc=Yes | ||
− | |max mem= | + | |max mem=? GiB |
|controllers=2 | |controllers=2 | ||
|channels=6 | |channels=6 | ||
− | |max bandwidth= | + | |max bandwidth=119.21 GiB/s |
− | |bandwidth schan= | + | |bandwidth schan=19.87 GiB/s |
− | |bandwidth dchan= | + | |bandwidth dchan=39.74 GiB/s |
− | |bandwidth qchan= | + | |bandwidth qchan=79.47 GiB/s |
− | |bandwidth hchan= | + | |bandwidth hchan=119.21 GiB/s |
}} | }} | ||
== Expansions == | == Expansions == | ||
− | {{expansions | + | {{expansions |
− | + | | pcie revision = 3.0 | |
− | + | | pcie lanes = 48 | |
− | + | | pcie config = x16 | |
− | |pcie revision=3.0 | + | | pcie config 2 = x8 |
− | |pcie lanes=48 | + | | pcie config 3 = x4 |
− | |pcie config= | ||
− | |pcie config 2=x8 | ||
− | |pcie config 3=x4 | ||
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}} | }} | ||
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|fastmem=No | |fastmem=No | ||
|ivmd=Yes | |ivmd=Yes | ||
− | |intelnodecontroller= | + | |intelnodecontroller=Yes |
|intelnode=Yes | |intelnode=Yes | ||
|kpt=Yes | |kpt=Yes | ||
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|amdpb2=No | |amdpb2=No | ||
|amdpbod=No | |amdpbod=No | ||
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}} | }} |
Facts about "Xeon Gold 6254 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 6254 - Intel#pcie + |
base frequency | 3,100 MHz (3.1 GHz, 3,100,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
chipset | Lewisburg + |
clock multiplier | 31 + |
core count | 18 + |
core family | 6 + |
core model | 85 + |
core name | Cascade Lake SP + |
core stepping | B0 + |
designer | Intel + |
family | Xeon Gold + |
first announced | April 2, 2019 + |
first launched | April 2, 2019 + |
full page name | intel/xeon gold/6254 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost + |
has intel deep learning boost | true + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 1,152 KiB (1,179,648 B, 1.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 576 KiB (589,824 B, 0.563 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 576 KiB (589,824 B, 0.563 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) + |
ldate | April 2, 2019 + |
main image | + |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 355.15 K (82 °C, 179.6 °F, 639.27 °R) + |
max cpu count | 4 + |
max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
max memory bandwidth | 131.13 GiB/s (134,277.12 MiB/s, 140.8 GB/s, 140,799.765 MB/s, 0.128 TiB/s, 0.141 TB/s) + |
max memory channels | 6 + |
microarchitecture | Cascade Lake + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | 6254 + |
name | Xeon Gold 6254 + |
package | FCLGA-3647 + |
part number | CD8069504194501 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 3,803.00 (€ 3,422.70, £ 3,080.43, ¥ 392,963.99) + |
release price (tray) | $ 3,803.00 (€ 3,422.70, £ 3,080.43, ¥ 392,963.99) + |
s-spec | SRF92 + |
s-spec (qs) | QRAM + |
series | 6200 + |
smp interconnect | UPI + |
smp interconnect links | 3 + |
smp interconnect rate | 10.4 GT/s + |
smp max ways | 4 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2933 + |
tdp | 200 W (200,000 mW, 0.268 hp, 0.2 kW) + |
technology | CMOS + |
thread count | 36 + |
turbo frequency (1 core) | 4,000 MHz (4 GHz, 4,000,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |