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|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
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|process=10 nm | |process=10 nm | ||
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|predecessor=Ice Lake (client) | |predecessor=Ice Lake (client) | ||
|predecessor link=intel/microarchitectures/ice lake (client) | |predecessor link=intel/microarchitectures/ice lake (client) | ||
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|contemporary=Sapphire Rapids | |contemporary=Sapphire Rapids | ||
|contemporary link=intel/microarchitectures/sapphire rapids | |contemporary link=intel/microarchitectures/sapphire rapids | ||
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|succession=Yes | |succession=Yes | ||
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'''Tiger Lake''' ('''TGL''') is [[Intel]]'s successor to {{\\|Ice Lake (client)|Ice Lake}}, a [[10 nm process|10nm]] [[microarchitecture]] for mainstream workstations, desktops, and mobile devices. | '''Tiger Lake''' ('''TGL''') is [[Intel]]'s successor to {{\\|Ice Lake (client)|Ice Lake}}, a [[10 nm process|10nm]] [[microarchitecture]] for mainstream workstations, desktops, and mobile devices. | ||
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== Process Technology== | == Process Technology== | ||
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* Core | * Core | ||
** {{\\|Sunny Cove}} '''➡''' {{\\|Willow Cove}} | ** {{\\|Sunny Cove}} '''➡''' {{\\|Willow Cove}} | ||
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** Up to 50% larger Level 3 cache - 3MB per core from 2MB per core | ** Up to 50% larger Level 3 cache - 3MB per core from 2MB per core | ||
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* GPU | * GPU | ||
** {{intel|Gen11|l=arch}} '''➡''' {{intel|Gen12|l=arch}} (Xe) | ** {{intel|Gen11|l=arch}} '''➡''' {{intel|Gen12|l=arch}} (Xe) |
Facts about "Tiger Lake - Microarchitectures - Intel"
codename | Tiger Lake + |
core count | 2 +, 4 +, 6 + and 8 + |
designer | Intel + |
first launched | September 2, 2020 + |
full page name | intel/microarchitectures/tiger lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Tiger Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |