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− | {{intel title| | + | {{intel title|Tigerlake|arch}} |
{{microarchitecture | {{microarchitecture | ||
− | |atype=CPU | + | | atype = CPU |
− | |name= | + | | name = Tigerlake |
− | |designer=Intel | + | | designer = Intel |
− | |manufacturer=Intel | + | | manufacturer = Intel |
− | |introduction= | + | | introduction = 2019 |
− | |process=10 nm | + | | phase-out = |
− | + | | process = 10 nm | |
− | | | + | |
− | + | | succession = Yes | |
− | + | | predecessor = Icelake | |
− | + | | predecessor link = intel/microarchitectures/icelake | |
− | + | | successor = | |
− | + | | successor link = | |
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− | |predecessor= | ||
− | |predecessor link=intel/microarchitectures/ | ||
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}} | }} | ||
− | ''' | + | '''Tigerlake''' ('''TGL''') is a planned [[microarchitecture]] by [[Intel]] as a successor to {{\\|Icelake}}. Tigerlake is expected to be fabricated using a [[10 nm process]]. Tigerlake is the "Optimization" microarchitecture as part of Intel's {{intel|PAO}} model. |
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== Process Technology== | == Process Technology== | ||
− | {{main|intel/microarchitectures/ | + | {{main|intel/microarchitectures/cannonlake#Process_Technology|l1=Cannonlake § Process Technology}} |
− | + | Tigerlake is set to use the same [[10 nm process]] that was designed for Cannonlake. | |
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− | === | + | == See also == |
− | + | * AMD {{amd|Zen 2|l=arch}} | |
− | * | ||
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Facts about "Tiger Lake - Microarchitectures - Intel"
codename | Tiger Lake + |
core count | 2 +, 4 +, 6 + and 8 + |
designer | Intel + |
first launched | September 2, 2020 + |
full page name | intel/microarchitectures/tiger lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Tiger Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |