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{{intel title|Saltwell|arch}} | {{intel title|Saltwell|arch}} | ||
{{microarchitecture | {{microarchitecture | ||
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| name = Saltwell | | name = Saltwell | ||
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| manufacturer = Intel | | manufacturer = Intel | ||
| introduction = 2011 | | introduction = 2011 | ||
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| pipeline = Yes | | pipeline = Yes | ||
| type = Superscalar | | type = Superscalar | ||
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| OoOE = No | | OoOE = No | ||
| speculative = No | | speculative = No | ||
| renaming = No | | renaming = No | ||
− | |isa=x86-64 | + | | isa = IA-32 |
+ | | isa 2 = x86-64 | ||
| stages = 16 | | stages = 16 | ||
| issues = 2 | | issues = 2 | ||
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| inst = Yes | | inst = Yes | ||
| feature = | | feature = | ||
− | | extension = | + | | extension = MMX |
− | | extension 2 = | + | | extension 2 = SSE |
− | | extension 3 = | + | | extension 3 = SSE2 |
− | | extension 4 = | + | | extension 4 = SSE3 |
− | | extension 5 | + | | extension 5 = SSSE3 |
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| cache = Yes | | cache = Yes | ||
− | | l1i = 32 | + | | l1i = 32 KB |
| l1i per = Core | | l1i per = Core | ||
| l1i desc = 8-way set associative | | l1i desc = 8-way set associative | ||
− | | l1d = 24 | + | | l1d = 24 KB |
| l1d per = Core | | l1d per = Core | ||
| l1d desc = 6-way set associative | | l1d desc = 6-way set associative | ||
− | | l2 = 512 | + | | l2 = 512 |
| l2 per = Cores | | l2 per = Cores | ||
| l2 desc = 8-way set associative | | l2 desc = 8-way set associative | ||
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! Platform !! Core !! Target | ! Platform !! Core !! Target | ||
|- | |- | ||
− | | {{intel|Medfield | + | | {{intel|Medfield}} || {{intel|Penwell}} || Smartphones |
|- | |- | ||
− | | {{intel|Cedar Trail}} || {{intel| | + | | {{intel|Cedar Trail}} || {{intel|Cedarview}}|| Netbooks |
|- | |- | ||
− | | {{intel|Clover Trail+}} || {{intel| | + | | {{intel|Clover Trail+}} || {{intel|Cloverview}} || Tablets |
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|- | |- | ||
| {{intel|Bordenville}} || {{intel|Centerton}} || Microservers | | {{intel|Bordenville}} || {{intel|Centerton}} || Microservers | ||
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| {{intel|Bordenville}} || {{intel|Briarwood}} || Microservers | | {{intel|Bordenville}} || {{intel|Briarwood}} || Microservers | ||
|- | |- | ||
− | | || {{intel|Berryville | + | | || {{intel|Berryville}} || CE (set-tops) |
|- | |- | ||
|} | |} | ||
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** Hardware prefetchers | ** Hardware prefetchers | ||
** L1 Cache: | ** L1 Cache: | ||
− | *** 32 | + | *** 32 KB 8-way [[set associative]] instruction |
**** 1 read and 1 write port | **** 1 read and 1 write port | ||
− | *** 24 | + | *** 24 KB 6-way set associative data |
**** 1 read and 1 write port | **** 1 read and 1 write port | ||
*** 8 transistors (instead of 6) to reduce voltage | *** 8 transistors (instead of 6) to reduce voltage | ||
*** Per core | *** Per core | ||
** L2 Cache: | ** L2 Cache: | ||
− | *** 512 | + | *** 512 KB 8-way set associative |
*** ECC | *** ECC | ||
− | *** Shrinkable from 512 | + | *** Shrinkable from 512 KB to 128 KB (2-way) |
*** 32B/cycle and 32 outstanding cache requests | *** 32B/cycle and 32 outstanding cache requests | ||
*** separate voltage rail, fixed @ 1.05V | *** separate voltage rail, fixed @ 1.05V | ||
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*** No level 3 cache | *** No level 3 cache | ||
** Non-Cache Shared State Memory | ** Non-Cache Shared State Memory | ||
− | *** | + | *** 256KB low-power SRAM |
*** separate voltage plane | *** separate voltage plane | ||
*** always-on block that stores architectural states while in various power saving modes | *** always-on block that stores architectural states while in various power saving modes | ||
** RAM | ** RAM | ||
− | *** Maximum of | + | *** Maximum of 1GB, 2 GB, and 4 GB |
*** dual 32-bit channels, 1 or 2 ranks per channel | *** dual 32-bit channels, 1 or 2 ranks per channel | ||
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* 2 Integer [[ALU]]s (1 for jumps, 1 for shifts) | * 2 Integer [[ALU]]s (1 for jumps, 1 for shifts) | ||
* 2 FP ALUs (1 adder, 1 for others) | * 2 FP ALUs (1 adder, 1 for others) | ||
− | * No Integer multiplier & divider | + | * No Integer multiplier & divider |
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=== Pipeline === | === Pipeline === | ||
Saltwell has an almost identical pipeline to {{intel|Bonnell|Bonnell's}} with a 16-stage pipeline with a 13-stage miss penalty. It's also still a dual-issue [[superscalar]] but with in-order execution. Reordering logic is was still omitted due to power and area restrictions. | Saltwell has an almost identical pipeline to {{intel|Bonnell|Bonnell's}} with a 16-stage pipeline with a 13-stage miss penalty. It's also still a dual-issue [[superscalar]] but with in-order execution. Reordering logic is was still omitted due to power and area restrictions. | ||
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* '''{{intel|Briarwood}}''' - SoCs for Microservers | * '''{{intel|Briarwood}}''' - SoCs for Microservers | ||
* '''{{intel|Berryville}}''' - SoCs for consumer electronics (e.g. set-tops) | * '''{{intel|Berryville}}''' - SoCs for consumer electronics (e.g. set-tops) | ||
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Facts about "Saltwell - Microarchitectures - Intel"
codename | Saltwell + |
core count | 1 + and 2 + |
designer | Intel + |
first launched | 2011 + |
full page name | intel/microarchitectures/saltwell + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Saltwell + |
phase-out | 2013 + |
pipeline stages | 16 + |
process | 32 nm (0.032 μm, 3.2e-5 mm) + |