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{{intel title|Rocket Lake|arch}} | {{intel title|Rocket Lake|arch}} | ||
{{microarchitecture | {{microarchitecture | ||
− | |atype= | + | |atype=APU |
|name=Rocket Lake | |name=Rocket Lake | ||
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
− | |||
|process=14 nm | |process=14 nm | ||
|cores=4 | |cores=4 | ||
− | |cores | + | |cores 5=6 |
− | |cores | + | |cores 9=8 |
+ | |cores 13=10 | ||
|type=Superscalar | |type=Superscalar | ||
|type 2=Superpipeline | |type 2=Superpipeline | ||
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|extension 29=SGX | |extension 29=SGX | ||
|extension 30=MPX | |extension 30=MPX | ||
− | |||
− | |||
|l1i=48 KiB | |l1i=48 KiB | ||
|l1i per=core | |l1i per=core | ||
− | |l1i desc= | + | |l1i desc=8-way set associative |
|l1d=32 KiB | |l1d=32 KiB | ||
|l1d per=core | |l1d per=core | ||
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|l2=512 KiB | |l2=512 KiB | ||
|l2 per=core | |l2 per=core | ||
− | |l2 desc= | + | |l2 desc=4-way set associative |
|l3=2 MiB | |l3=2 MiB | ||
|l3 per=core | |l3 per=core | ||
− | |l3 desc=16-way set associative | + | |l3 desc=Up to 16-way set associative |
− | | | + | |l4=128 MiB |
+ | |l4 per=package | ||
+ | |l4 desc=on Iris Pro GPUs only | ||
|predecessor=Comet Lake | |predecessor=Comet Lake | ||
|predecessor link=intel/microarchitectures/comet lake | |predecessor link=intel/microarchitectures/comet lake | ||
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|contemporary link=intel/microarchitectures/tiger_lake | |contemporary link=intel/microarchitectures/tiger_lake | ||
}} | }} | ||
− | '''Rocket Lake''' ('''RKL''') is a [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Comet Lake}} for desktops and | + | '''Rocket Lake''' ('''RKL''') is a planned [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Comet Lake}} for desktops and high-performance mobile devices. |
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== Brands == | == Brands == | ||
− | Intel | + | Intel is expected to release Rocket Lake under 3 main brand families: |
{| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;" | {| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;" | ||
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! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="6" | Differentiating Features | ! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="6" | Differentiating Features | ||
|- | |- | ||
− | ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2 | + | ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]] |
|- | |- | ||
− | | [[File:core | + | | [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || {{intel|Core i3}} || Low-end Performance || || |
|- | |- | ||
− | | [[File:core | + | | [[File:core i5 logo (2015).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || Mid-range Performance || || |
|- | |- | ||
− | | [[File:core | + | | [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || High-end Performance || || |
− | |||
− | |||
|} | |} | ||
== Release Dates == | == Release Dates == | ||
− | + | Rocket Lake is expected to be released in Q1 2021. | |
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== Compatibility== | == Compatibility== | ||
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| [[ICC]] || <code>-march=?</code> || <code>-mtune=?</code> | | [[ICC]] || <code>-march=?</code> || <code>-mtune=?</code> | ||
|- | |- | ||
− | | [[GCC]] || <code>-march= | + | | [[GCC]] || <code>-march=?</code> || <code>-mtune=?</code> |
|- | |- | ||
| [[LLVM]] || <code>-march=?</code> || <code>-mtune=?</code> | | [[LLVM]] || <code>-march=?</code> || <code>-mtune=?</code> | ||
|- | |- | ||
− | | [[Visual Studio]] || <code>/arch: | + | | [[Visual Studio]] || <code>/arch:AVX2</code> || <code>/?</code> |
|} | |} | ||
=== CPUID === | === CPUID === | ||
− | {{ | + | {{empty section}} |
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== Architecture == | == Architecture == |
Facts about "Rocket Lake - Microarchitectures - Intel"
codename | Rocket Lake + |
core count | 4 +, 6 + and 8 + |
designer | Intel + |
first launched | March 16, 2021 + |
full page name | intel/microarchitectures/rocket lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Rocket Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |