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|core name 3=Kaby Lake R | |core name 3=Kaby Lake R | ||
|core name 4=Kaby Lake H | |core name 4=Kaby Lake H | ||
− | |core name 5=Kaby Lake | + | |core name 5=Kaby Lake M |
|core name 6=Kaby Lake S | |core name 6=Kaby Lake S | ||
|core name 7=Kaby Lake DT | |core name 7=Kaby Lake DT | ||
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}} | }} | ||
[[File:7th Gen Core-i7-badge.png|thumb|right|175px|Kaby Lake is Intel's 7th Generation {{intel|Core i7}} MPUs.]] | [[File:7th Gen Core-i7-badge.png|thumb|right|175px|Kaby Lake is Intel's 7th Generation {{intel|Core i7}} MPUs.]] | ||
− | '''Kaby Lake''' ('''KBL''') is [[Intel]]'s successor to {{\\|Skylake}}, an enhanced [[14 nm process]] [[microarchitecture]] for mainstream desktops and mobile devices. Kaby Lake is the first "Optimization" released as part of Intel's {{intel|PAO}} model. The microarchitecture was developed by Intel's R&D center in [[wikipedia:Haifa, Israel|Haifa, Israel]]. {{\\|Cannon Lake}} was originally set to replace {{\\|Skylake}} as the next microarchitecture using a [[10 nm process]], however Intel later revised their roadmap to include Kaby Lake (with Cannon Lake being pushed back to [[ | + | '''Kaby Lake''' ('''KBL''') is [[Intel]]'s successor to {{\\|Skylake}}, an enhanced [[14 nm process]] [[microarchitecture]] for mainstream desktops and mobile devices. Kaby Lake is the first "Optimization" released as part of Intel's {{intel|PAO}} model. The microarchitecture was developed by Intel's R&D center in [[wikipedia:Haifa, Israel|Haifa, Israel]]. {{\\|Cannon Lake}} was originally set to replace {{\\|Skylake}} as the next microarchitecture using a [[10 nm process]], however Intel later revised their roadmap to include Kaby Lake (with Cannon Lake being pushed back to [[2017]]). |
For desktop and mobile, Kaby Lake is branded as 7th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}. and {{intel|Core i7}} processors. For workstation class processors, Intel branded it as {{intel|Xeon E3|Xeon E3 v6}}. There are no Kaby Lake-based server microprocessors. | For desktop and mobile, Kaby Lake is branded as 7th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}. and {{intel|Core i7}} processors. For workstation class processors, Intel branded it as {{intel|Xeon E3|Xeon E3 v6}}. There are no Kaby Lake-based server microprocessors. | ||
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{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
− | ! Core !! Abbrev !! | + | ! Core !! Abbrev !! Description !! Graphics !! Target |
|- | |- | ||
− | | {{intel|Kaby Lake Y|l=core}} || KBL-Y | + | | {{intel|Kaby Lake Y|l=core}} || KBL-Y || Extremely low power || GT2 || 2-in-1s detachable, tablets, and computer sticks |
|- | |- | ||
− | | {{intel|Kaby Lake U|l=core}} || KBL-U | + | | {{intel|Kaby Lake U|l=core}} || KBL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room |
|- | |- | ||
− | | {{intel|Kaby Lake R|l=core}} || KBL-R | + | | {{intel|Kaby Lake R|l=core}} || KBL-R || Ultra-low Power || GT2 || Kaby Lake U Refresh |
|- | |- | ||
− | | {{intel|Kaby Lake H|l=core}} || KBL-H | + | | {{intel|Kaby Lake H|l=core}} || KBL-H || High-performance Graphics || GT2/GT3 || Ultimate mobile performance, mobile workstations |
|- | |- | ||
− | | {{intel|Kaby Lake S|l=core}} || KBL-S | + | | {{intel|Kaby Lake S|l=core}} || KBL-S || Performance-optimized lifestyle || GT2/GT3 || Desktop performance to value, AiOs, and minis |
|- | |- | ||
− | | {{intel|Kaby Lake G|l=core}} || KBL-G | + | | {{intel|Kaby Lake G|l=core}} || KBL-G || Gaming Chip || AMD [Vega/Polaris]? || Kaby Lake + ? |
|- | |- | ||
− | | {{intel|Kaby Lake X|l=core}} || KBL-X | + | | {{intel|Kaby Lake X|l=core}} || KBL-X || Extreme Performance || || High-end desktops & enthusiasts market |
|- | |- | ||
− | | {{intel|Kaby Lake DT|l=core}} || KBL-DT | + | | {{intel|Kaby Lake DT|l=core}} || KBL-DT || Workstation || GT2 || Workstations & entry-level servers |
|} | |} | ||
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=== CPUID === | === CPUID === | ||
− | {| class="wikitable tc1 tc2 tc3 tc4 | + | {| class="wikitable tc1 tc2 tc3 tc4" |
− | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model | + | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model |
|- | |- | ||
− | | rowspan="2" | {{intel|Kaby Lake Y|Y|l=core}}/{{intel|Kaby Lake U|U|l=core}}/{{intel|Kaby Lake R|R|l=core}} || 0 || 0x6 || 0x8 || 0xE | + | | rowspan="2" | {{intel|Kaby Lake Y|Y|l=core}}/{{intel|Kaby Lake U|U|l=core}}/{{intel|Kaby Lake R|R|l=core}} || 0 || 0x6 || 0x8 || 0xE |
|- | |- | ||
− | | colspan=" | + | | colspan="4" | Family 6 Model 142 |
|- | |- | ||
− | | rowspan="2" | {{intel|Kaby Lake DT|DT|l=core}}/{{intel|Kaby Lake H|H|l=core}}/{{intel|Kaby Lake S|S|l=core}}/{{intel|Kaby Lake X|X|l=core}} || 0 || 0x6 || 0x9 || 0xE | + | | rowspan="2" | {{intel|Kaby Lake DT|DT|l=core}}/{{intel|Kaby Lake H|H|l=core}}/{{intel|Kaby Lake S|S|l=core}}/{{intel|Kaby Lake X|X|l=core}} || 0 || 0x6 || 0x9 || 0xE |
|- | |- | ||
− | | colspan=" | + | | colspan="4" | Family 6 Model 158 |
|} | |} | ||
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* Families | * Families | ||
− | ** {{intel|Core i3}} processors dropped support for ECC memory | + | ** {{intel|Core i3}} processors dropped support for ECC memory (except for Embedded models) |
** {{intel|Pentium (2009)|Pentium}} desktop processors now have {{intel|Hyper-Threading}} support (note that Mobile Pentium already had that feature.) | ** {{intel|Pentium (2009)|Pentium}} desktop processors now have {{intel|Hyper-Threading}} support (note that Mobile Pentium already had that feature.) | ||
** {{intel|Pentium (2009)|Pentium}} desktop & mobile processors now have Memory Protection ({{intel|MPX}}) and {{intel|OS Guard}} support | ** {{intel|Pentium (2009)|Pentium}} desktop & mobile processors now have Memory Protection ({{intel|MPX}}) and {{intel|OS Guard}} support | ||
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**** fixed partition | **** fixed partition | ||
*** 1G page translations: | *** 1G page translations: | ||
− | **** 4 entries; | + | **** 4 entries; fully associative |
**** fixed partition | **** fixed partition | ||
** STLB | ** STLB | ||
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== Core == | == Core == | ||
− | |||
− | |||
− | |||
=== Pipeline === | === Pipeline === | ||
{{main|intel/microarchitectures/skylake#Pipeline|l1=Skylake § Pipeline}} | {{main|intel/microarchitectures/skylake#Pipeline|l1=Skylake § Pipeline}} | ||
Kaby Lake's pipeline is identical to {{\\|Skylake#Pipeline|Skylake's}}. | Kaby Lake's pipeline is identical to {{\\|Skylake#Pipeline|Skylake's}}. | ||
+ | |||
+ | ==== Scheduler Ports & Execution Units ==== | ||
+ | <table class="wikitable"> | ||
+ | <tr><th colspan="2">Scheduler Ports Designation</th></tr> | ||
+ | <tr><th rowspan="5">Port 0</th><td>Integer/Vector Arithmetic, Multiplication, Logic, Shift, and String ops</td></tr> | ||
+ | <tr><td>[[FP]] Add, [[Multiply]], [[FMA]]</td></tr> | ||
+ | <tr><td>Integer/FP Division and [[Square Root]]</td></tr> | ||
+ | <tr><td>[[AES]] Encryption</td></tr> | ||
+ | <tr><td>Branch2</td></tr> | ||
+ | <tr><th rowspan="2">Port 1</th><td>Integer/Vector Arithmetic, Multiplication, Logic, Shift, and Bit Scanning</td></tr> | ||
+ | <tr><td>[[FP]] Add, [[Multiply]], [[FMA]]</td></tr> | ||
+ | <tr><th rowspan="3">Port 5</th><td>Integer/Vector Arithmetic, Logic</td></tr> | ||
+ | <tr><td>Vector Permute</td></tr> | ||
+ | <tr><td>[[x87]] FP Add, Composite Int, CLMUL</td></tr> | ||
+ | <tr><th rowspan="2">Port 6</th><td>Integer Arithmetic, Logic, Shift</td></tr> | ||
+ | <tr><td>Branch</td></tr> | ||
+ | <tr><th>Port 2</th><td>Load, AGU</td></tr> | ||
+ | <tr><th>Port 3</th><td>Load, AGU</td></tr> | ||
+ | <tr><th>Port 4</th><td>Store, AGU</td></tr> | ||
+ | <tr><th>Port 7</th><td>AGU</td></tr> | ||
+ | </table> | ||
+ | |||
+ | {| class="wikitable collapsible collapsed" | ||
+ | |- | ||
+ | ! colspan="3" | Execution Units | ||
+ | |- | ||
+ | ! Execution Unit !! # of Units !! Instructions | ||
+ | |- | ||
+ | | ALU || 4 || add, and, cmp, or, test, xor, movzx, movsx, mov, (v)movdqu, (v)movdqa, (v)movap*, (v)movup* | ||
+ | |- | ||
+ | | DIV || 1 || divp*, divs*, vdiv*, sqrt*, vsqrt*, rcp*, vrcp*, rsqrt*, idiv | ||
+ | |- | ||
+ | | Shift || 2 || sal, shl, rol, adc, sarx, adcx, adox, etc... | ||
+ | |- | ||
+ | | Shuffle || 1 || (v)shufp*, vperm*, (v)pack*, (v)unpck*, (v)punpck*, (v)pshuf*, (v)pslldq, (v)alignr, (v)pmovzx*, vbroadcast*, (v)pslldq, (v)psrldq, (v)pblendw | ||
+ | |- | ||
+ | | Slow Int || 1 || mul, imul, bsr, rcl, shld, mulx, pdep, etc... | ||
+ | |- | ||
+ | | Bit Manipulation || 2 || andn, bextr, blsi, blsmsk, bzhi, etc | ||
+ | |- | ||
+ | | FP Mov || 1 || (v)movsd/ss, (v)movd gpr | ||
+ | |- | ||
+ | | SIMD Misc || 1 || STTNI, (v)pclmulqdq, (v)psadw, vector shift count in xmm | ||
+ | |- | ||
+ | | Vec ALU || 3 || (v)pand, (v)por, (v)pxor, (v)movq, (v)movq, (v)movap*, (v)movup*, (v)andp*, (v)orp*, (v)paddb/w/d/q, (v)blendv*, (v)blendp*, (v)pblendd | ||
+ | |- | ||
+ | | Vec Shift || 2 || (v)psllv*, (v)psrlv*, vector shift count in imm8 | ||
+ | |- | ||
+ | | Vec Add || 2 || (v)addp*, (v)cmpp*, (v)max*, (v)min*, (v)padds*, (v)paddus*, (v)psign, (v)pabs, (v)pavgb, (v)pcmpeq*, (v)pmax, (v)cvtps2dq, (v)cvtdq2ps, (v)cvtsd2si, (v)cvtss2si | ||
+ | |- | ||
+ | | Vec Mul || 2 || (v)mul*, (v)pmul*, (v)pmadd* | ||
+ | |- | ||
+ | |colspan="3" | This table was taken verbatim from the Intel manual. Execution unit mapping to {{x86|MMX|MMX instructions}} are not included. | ||
+ | |} | ||
== Configurability == | == Configurability == | ||
− | Kaby Lake builds upon the Skylake architecture, most dies are slight | + | Kaby Lake builds upon the Skylake architecture, most dies are slight enchantments of their Skylake counterparts. The biggest change is the removal of the high performance quad core GT4 die, presumably because of low demand. And the introduction of the first low power quad core processor. |
<gallery widths=300px heights=150px caption="Physical Layout Breakdown" style="float:right"> | <gallery widths=300px heights=150px caption="Physical Layout Breakdown" style="float:right"> | ||
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=== Overclocking === | === Overclocking === | ||
See {{intel|Skylake#Overclocking|Skylake §Overclocking|l=arch}}. | See {{intel|Skylake#Overclocking|Skylake §Overclocking|l=arch}}. | ||
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== Die == | == Die == | ||
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* 4 CPU cores + 24 GPU EUs | * 4 CPU cores + 24 GPU EUs | ||
− | : [[File:kaby lake (quad core).png | + | : [[File:kaby lake (quad core).png|650px]] |
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<tr class="comptable-header"><th class="unsortable">Model</th><th>Launched</th><th data-sort-type="currency">Price</th><th>Family</th><th>Platform</th><th>Core</th><th data-sort-type="number">Cores</th><th data-sort-type="number">Threads</th><th data-sort-type="number">L3$</th><th data-sort-type="number">L4$</th><th data-sort-type="number">TDP</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th data-sort-type="number">Max Mem</th><th>Name</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th>[[ECC]]</th><th>{{intel|turbo boost|TBT}}</th><th>HT</th><th>AVX</th><th>AVX2</th><th>TXT</th><th>TSX</th><th>vPro</th><th>VT-d</th></tr> | <tr class="comptable-header"><th class="unsortable">Model</th><th>Launched</th><th data-sort-type="currency">Price</th><th>Family</th><th>Platform</th><th>Core</th><th data-sort-type="number">Cores</th><th data-sort-type="number">Threads</th><th data-sort-type="number">L3$</th><th data-sort-type="number">L4$</th><th data-sort-type="number">TDP</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th data-sort-type="number">Max Mem</th><th>Name</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th>[[ECC]]</th><th>{{intel|turbo boost|TBT}}</th><th>HT</th><th>AVX</th><th>AVX2</th><th>TXT</th><th>TSX</th><th>vPro</th><th>VT-d</th></tr> | ||
<tr class="comptable-header comptable-header-sep"><th> </th><th colspan="25">[[Uniprocessors]]</th></tr> | <tr class="comptable-header comptable-header-sep"><th> </th><th colspan="25">[[Uniprocessors]]</th></tr> | ||
− | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Kaby Lake]] [[max cpu count::1]] [[core name::!Kaby Lake R | + | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Kaby Lake]] [[max cpu count::1]] [[core name::!Kaby Lake R]] |
|?full page name | |?full page name | ||
|?model number | |?model number | ||
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<tr class="comptable-header comptable-header-sep"><th> </th><th colspan="25">8th Generation ({{intel|Kaby Lake R|Kaby Lake Refresh|l=core}})</th></tr> | <tr class="comptable-header comptable-header-sep"><th> </th><th colspan="25">8th Generation ({{intel|Kaby Lake R|Kaby Lake Refresh|l=core}})</th></tr> | ||
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Kaby Lake]] [[max cpu count::1]] [[core name::Kaby Lake R]] | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Kaby Lake]] [[max cpu count::1]] [[core name::Kaby Lake R]] | ||
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|?full page name | |?full page name | ||
|?model number | |?model number | ||
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* [[:File:kaby-lake-r-product-brief.pdf|Kaby Lake R Product Brief]] | * [[:File:kaby-lake-r-product-brief.pdf|Kaby Lake R Product Brief]] | ||
* [[:File:8th-gen-intel-core-product-overview.pdf|8th generation Core family product overview]] | * [[:File:8th-gen-intel-core-product-overview.pdf|8th generation Core family product overview]] | ||
− | |||
− | == | + | == References == |
* Intel Developer Forum 2015, San Francisco, August 18-20, 2015 | * Intel Developer Forum 2015, San Francisco, August 18-20, 2015 | ||
* Intel Technology and Manufacturing Day, March 28, 2017 | * Intel Technology and Manufacturing Day, March 28, 2017 | ||
* 8th Generation core announcement, August 21, 2017 | * 8th Generation core announcement, August 21, 2017 | ||
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== Artwork == | == Artwork == |
Facts about "Kaby Lake - Microarchitectures - Intel"
codename | Kaby Lake + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | August 30, 2016 + |
full page name | intel/microarchitectures/kaby lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Kaby Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |