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Latest revision | Your text | ||
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|stages min=14 | |stages min=14 | ||
|stages max=19 | |stages max=19 | ||
− | |isa=x86-64 | + | |isa=x86-16 |
+ | |isa 2=x86-32 | ||
+ | |isa 3=x86-64 | ||
|extension=MOVBE | |extension=MOVBE | ||
|extension 2=MMX | |extension 2=MMX | ||
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|extension 29=SGX | |extension 29=SGX | ||
|extension 30=MPX | |extension 30=MPX | ||
+ | |extension 31=AVX-512 | ||
|l1i=32 KiB | |l1i=32 KiB | ||
|l1i per=core | |l1i per=core | ||
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|core name=Kaby Lake Y | |core name=Kaby Lake Y | ||
|core name 2=Kaby Lake U | |core name 2=Kaby Lake U | ||
− | |core name 3=Kaby Lake | + | |core name 3=Kaby Lake H |
− | |core name 4=Kaby Lake | + | |core name 4=Kaby Lake S |
− | |core name 5=Kaby Lake | + | |core name 5=Kaby Lake DT |
− | |core name 6 | + | |core name 6=Kaby Lake X |
− | |||
− | |||
|predecessor=Skylake | |predecessor=Skylake | ||
|predecessor link=intel/microarchitectures/skylake | |predecessor link=intel/microarchitectures/skylake | ||
|successor=Coffee Lake | |successor=Coffee Lake | ||
|successor link=intel/microarchitectures/coffee lake | |successor link=intel/microarchitectures/coffee lake | ||
− | |successor 2= | + | |successor 2=Cannonlake |
− | |successor 2 link=intel/microarchitectures/ | + | |successor 2 link=intel/microarchitectures/cannonlake |
+ | |pipeline=Yes | ||
+ | |OoOE=Yes | ||
+ | |issues=5 | ||
+ | |inst=Yes | ||
+ | |cache=Yes | ||
+ | |core names=Yes | ||
+ | |succession=Yes | ||
}} | }} | ||
− | [[File:7th Gen Core-i7-badge.png|thumb|right| | + | [[File:7th Gen Core-i7-badge.png|thumb|right|250px|Kaby Lake is Intel's 7th Generation {{intel|Core i7}} MPUs.]] |
− | '''Kaby Lake''' ('''KBL''') is [[Intel]]'s successor to {{\\|Skylake}}, an enhanced [[14 nm process]] [[microarchitecture]] for mainstream desktops and mobile devices. Kaby Lake is the first "Optimization" released as part of Intel's {{intel|PAO}} model. The microarchitecture was developed by Intel's R&D center in [[wikipedia:Haifa, Israel|Haifa, Israel]]. {{\\| | + | '''Kaby Lake''' ('''KBL''') is [[Intel]]'s successor to {{\\|Skylake}}, an enhanced [[14 nm process]] [[microarchitecture]] for mainstream desktops, servers, and mobile devices. Kaby Lake is the first "Optimization" released as part of Intel's {{intel|PAO}} model. The microarchitecture was developed by Intel's R&D center in [[wikipedia:Haifa, Israel|Haifa, Israel]]. {{\\|Cannonlake}} was originally set to replace {{\\|Skylake}} as the next microarchitecture using a [[10 nm process]], however Intel later revised their roadmap to include Kaby Lake (with Cannonlake being pushed back to [[2017]]). |
− | For desktop and mobile, Kaby Lake is branded as 7th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}. and {{intel|Core i7}} processors. For | + | For desktop and mobile, Kaby Lake is branded as 7th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}. and {{intel|Core i7}} processors. For server class processors, Intel branded it as {{intel|Xeon E3|Xeon E3 v6}}, {{intel|Xeon E5|Xeon E5 v6}}, and {{intel|Xeon E7|Xeon E7 v6}}. |
== Codenames == | == Codenames == | ||
{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
− | ! Core !! Abbrev !! | + | ! Core !! Abbrev !! Description !! Graphics !! Target |
|- | |- | ||
− | | {{intel|Kaby Lake Y|l=core}} || KBL-Y | + | | {{intel|Kaby Lake Y|l=core}} || KBL-Y || Extremely low power || GT2 || 2-in-1s detachable, tablets, and computer sticks |
|- | |- | ||
− | | {{intel|Kaby Lake U|l=core}} || KBL-U | + | | {{intel|Kaby Lake U|l=core}} || KBL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room |
|- | |- | ||
− | | {{intel|Kaby Lake | + | | {{intel|Kaby Lake H|l=core}} || KBL-H || High-performance Graphics || GT2/GT3 || Ultimate mobile performance, mobile workstations |
|- | |- | ||
− | | {{intel|Kaby Lake | + | | {{intel|Kaby Lake S|l=core}} || KBL-S || Performance-optimized lifestyle || GT2/GT3 || Desktop performance to value, AiOs, and minis |
|- | |- | ||
− | | {{intel|Kaby Lake | + | | {{intel|Kaby Lake R|l=core}} || KBL-R || || || Kaby Lake U Refresh? |
|- | |- | ||
− | | {{intel|Kaby Lake G|l=core}} || KBL-G || | + | | {{intel|Kaby Lake G|l=core}} || KBL-G || || || Kaby Lake + ? |
|- | |- | ||
− | | {{intel|Kaby Lake X|l=core}} || KBL-X | + | | {{intel|Kaby Lake X|l=core}} || KBL-X || Extreme Performance || || High-end desktops & enthusiasts market |
|- | |- | ||
− | | {{intel|Kaby Lake DT|l=core}} || KBL-DT | + | | {{intel|Kaby Lake DT|l=core}} || KBL-DT || Workstation || GT2 || Workstations & entry-level servers |
|} | |} | ||
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! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]] | ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]] | ||
|- | |- | ||
− | | [[File:intel celeron (2015).png|50px | + | | [[File:intel celeron (2015).png|50px]] || {{intel|Celeron}} || style="text-align: left;" | Entry-level Budget || [[dual-core|dual]] || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘ |
|- | |- | ||
− | | rowspan="2" | [[File:intel pentium (2015).png|50px | + | | rowspan="2" | [[File:intel pentium (2015).png|50px]] || rowspan="2" | {{intel|Pentium (2009)|Pentium}} || style="text-align: left;" | Budget (Mobile) || rowspan="2" | dual || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘ |
|- | |- | ||
− | | style="text-align: left;" | Budget (Desktop) || | + | | style="text-align: left;" | Budget (Desktop) || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘ || style="background-color: #d6ffd8;" | ✔ |
|- | |- | ||
− | | rowspan="2" | [[File: | + | | rowspan="2" | [[File:core i3 logo (2015).png|50px]] || rowspan="2" | {{intel|Core i3}} || style="text-align: left;" | Low-end Performance || rowspan="2" | dual || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘ |
|- | |- | ||
− | | style="text-align: left;" | | + | | style="text-align: left;" | Low-end Performance (E Series) || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘ || style="background-color: #d6ffd8;" | ✔ |
|- | |- | ||
− | | rowspan="2" | [[File:core | + | | rowspan="2" | [[File:core i5 logo (2015).png|50px]] || rowspan="2" | {{intel|Core i5}} || rowspan="2" style="text-align: left;" | Mid-range Performance || dual || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘ |
|- | |- | ||
− | | style=" | + | |[[quad-core|quad]] || style="background-color: #ffdad6;" | ✘ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘ |
|- | |- | ||
− | | rowspan=" | + | | rowspan="2" | [[File:core i7 logo (2015).png|50px]] || rowspan="2" | {{intel|Core i7}} || rowspan="2" style="text-align: left;" | High-end Performance || dual || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘ |
|- | |- | ||
− | | | + | |quad || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘ |
|- | |- | ||
− | + | | [[File:xeon logo (2015).png|50px]] || {{intel|Xeon E3}} || style="text-align: left;" | Workstation high-performance/dense servers || quad || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ | |
− | |||
− | |||
− | |||
− | |||
− | |||
− | | [[File:xeon logo (2015).png|50px | ||
|} | |} | ||
== Release Dates == | == Release Dates == | ||
− | Kaby Lake is set to be released in two phases. The first phase was announced in August of [[2016]] and was primarily aimed at various low-power consumer products such as light notebooks and 2-in-1s. Those devices are powered by {{intel|Kaby Lake Y|l=core}} and {{intel|Kaby Lake U|l=core}} CPUs. Intel released mainstream {{intel|Kaby Lake S|l=core}} and {{intel|Kaby Lake H|l=core}} processors on January 3, [[2017]] in time for CES 2017. | + | Kaby Lake is set to be released in two phases. The first phase was announced in August of [[2016]] and was primarily aimed at various low-power consumer products such as light notebooks and 2-in-1s. Those devices are powered by {{intel|Kaby Lake Y|l=core}} and {{intel|Kaby Lake U|l=core}} CPUs. Intel released mainstream {{intel|Kaby Lake S|l=core}} and {{intel|Kaby Lake H|l=core}} processors on January 3, [[2017]] in time for CES 2017. Additionally, {{intel|Kaby Lake X|l=core}} are expecting to be released in late August during Gamescom 2017. |
− | |||
− | |||
== Process Technology == | == Process Technology == | ||
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== Compatibility == | == Compatibility == | ||
− | There are no official drivers by Intel for [[Windows 7]] or [[Windows 8]]. | + | There are no official drivers by Intel for [[Windows 7]] or [[Windows 8]]. Microsoft announced that only [[Windows 10]] will have support for Kaby Lake. [[Linux]] added initial support for Kaby Lake starting with Linux Kernel 4.5. |
{| class="wikitable" | {| class="wikitable" | ||
! Vendor !! OS !! Version !! Notes | ! Vendor !! OS !! Version !! Notes | ||
|- | |- | ||
− | | rowspan="3" | | + | | rowspan="3" | Microsoft || rowspan="3" | Windows || style="background-color: #ffdad6;" | Windows 7 || No Support |
|- | |- | ||
| style="background-color: #ffdad6;" | Windows 8 || No Support | | style="background-color: #ffdad6;" | Windows 8 || No Support | ||
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|- | |- | ||
| [[Visual Studio]] || <code>/arch:AVX2</code> || <code>/tune:skylake</code> | | [[Visual Studio]] || <code>/arch:AVX2</code> || <code>/tune:skylake</code> | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|} | |} | ||
== Architecture == | == Architecture == | ||
{{see also|intel/microarchitectures/skylake#Key_changes_from_Broadwell|l1=Skylake § Key changes from Broadwell}} | {{see also|intel/microarchitectures/skylake#Key_changes_from_Broadwell|l1=Skylake § Key changes from Broadwell}} | ||
+ | [[File:kaby lake silicon wafer.jpg|right|thumb|Kaby Lake silicon [[wafer]] with 7th generation core processor dies.]] | ||
While there is no change in pure IPC over Skylake and the actual microarchitecture is largely the same, Intel introduced a number of enhancements in Kaby Lake. Note that because of the improvements done to the process and the uplift in binning, it is the mostly the ultra-low power (i.e. mobile) processors that will see the most substantial gain. Likewise, the high-end models will see very little gain. The enhanced manufacturing process allowed Kaby Lake chips to be highly [[overclockable]] with models such as the [[Core i7-7700K]] capable of comfortably reaching 5 GHz for many people with a reasonable cooling setup. | While there is no change in pure IPC over Skylake and the actual microarchitecture is largely the same, Intel introduced a number of enhancements in Kaby Lake. Note that because of the improvements done to the process and the uplift in binning, it is the mostly the ultra-low power (i.e. mobile) processors that will see the most substantial gain. Likewise, the high-end models will see very little gain. The enhanced manufacturing process allowed Kaby Lake chips to be highly [[overclockable]] with models such as the [[Core i7-7700K]] capable of comfortably reaching 5 GHz for many people with a reasonable cooling setup. | ||
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*** Sunrise Point is still compatible (may need firmware update) | *** Sunrise Point is still compatible (may need firmware update) | ||
** Added support for {{intel|Optane}} Technology | ** Added support for {{intel|Optane}} Technology | ||
− | |||
− | |||
− | |||
− | |||
* Interfaces | * Interfaces | ||
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* {{intel|Gen 9.5|l=arch}} GPUs | * {{intel|Gen 9.5|l=arch}} GPUs | ||
− | |||
** New native hardware support for 4K HEVC/VP9 (See [[#Graphics|§ Graphics]]) | ** New native hardware support for 4K HEVC/VP9 (See [[#Graphics|§ Graphics]]) | ||
** {{intel|HD Graphics 510}} '''→''' {{intel|HD Graphics 610}} (12 Execution Units, no change) | ** {{intel|HD Graphics 510}} '''→''' {{intel|HD Graphics 610}} (12 Execution Units, no change) | ||
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* Families | * Families | ||
− | ** {{intel|Core i3}} processors dropped support for ECC memory | + | ** {{intel|Core i3}} processors dropped support for ECC memory (except for Embedded models) |
** {{intel|Pentium (2009)|Pentium}} desktop processors now have {{intel|Hyper-Threading}} support (note that Mobile Pentium already had that feature.) | ** {{intel|Pentium (2009)|Pentium}} desktop processors now have {{intel|Hyper-Threading}} support (note that Mobile Pentium already had that feature.) | ||
** {{intel|Pentium (2009)|Pentium}} desktop & mobile processors now have Memory Protection ({{intel|MPX}}) and {{intel|OS Guard}} support | ** {{intel|Pentium (2009)|Pentium}} desktop & mobile processors now have Memory Protection ({{intel|MPX}}) and {{intel|OS Guard}} support | ||
Line 258: | Line 241: | ||
==== Individual Core ==== | ==== Individual Core ==== | ||
− | <small>(Core identical to {{\\|Skylake | + | <small>(Core identical to {{\\|Skylake}})</small> |
− | [[File:skylake block diagram.svg | + | [[File:skylake block diagram.svg]] |
==== Gen9.5 ==== | ==== Gen9.5 ==== | ||
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**** fixed partition | **** fixed partition | ||
*** 1G page translations: | *** 1G page translations: | ||
− | **** 4 entries; | + | **** 4 entries; fully associative |
**** fixed partition | **** fixed partition | ||
** STLB | ** STLB | ||
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**** fixed partition | **** fixed partition | ||
<!-- ===================== END IF YOU CHANGE HERE, CHANGE ON SKYLAKE !! ============================= --> | <!-- ===================== END IF YOU CHANGE HERE, CHANGE ON SKYLAKE !! ============================= --> | ||
− | |||
− | |||
− | |||
== Core == | == Core == | ||
− | |||
− | |||
− | |||
=== Pipeline === | === Pipeline === | ||
{{main|intel/microarchitectures/skylake#Pipeline|l1=Skylake § Pipeline}} | {{main|intel/microarchitectures/skylake#Pipeline|l1=Skylake § Pipeline}} | ||
Kaby Lake's pipeline is identical to {{\\|Skylake#Pipeline|Skylake's}}. | Kaby Lake's pipeline is identical to {{\\|Skylake#Pipeline|Skylake's}}. | ||
− | == | + | ==== Scheduler Ports & Execution Units ==== |
+ | <table class="wikitable"> | ||
+ | <tr><th colspan="2">Scheduler Ports Designation</th></tr> | ||
+ | <tr><th rowspan="5">Port 0</th><td>Integer/Vector Arithmetic, Multiplication, Logic, Shift, and String ops</td></tr> | ||
+ | <tr><td>[[FP]] Add, [[Multiply]], [[FMA]]</td></tr> | ||
+ | <tr><td>Integer/FP Division and [[Square Root]]</td></tr> | ||
+ | <tr><td>[[AES]] Encryption</td></tr> | ||
+ | <tr><td>Branch2</td></tr> | ||
+ | <tr><th rowspan="2">Port 1</th><td>Integer/Vector Arithmetic, Multiplication, Logic, Shift, and Bit Scanning</td></tr> | ||
+ | <tr><td>[[FP]] Add, [[Multiply]], [[FMA]]</td></tr> | ||
+ | <tr><th rowspan="3">Port 5</th><td>Integer/Vector Arithmetic, Logic</td></tr> | ||
+ | <tr><td>Vector Permute</td></tr> | ||
+ | <tr><td>[[x87]] FP Add, Composite Int, CLMUL</td></tr> | ||
+ | <tr><th rowspan="2">Port 6</th><td>Integer Arithmetic, Logic, Shift</td></tr> | ||
+ | <tr><td>Branch</td></tr> | ||
+ | <tr><th>Port 2</th><td>Load, AGU</td></tr> | ||
+ | <tr><th>Port 3</th><td>Load, AGU</td></tr> | ||
+ | <tr><th>Port 4</th><td>Store, AGU</td></tr> | ||
+ | <tr><th>Port 7</th><td>AGU</td></tr> | ||
+ | </table> | ||
− | + | {| class="wikitable collapsible collapsed" | |
− | + | |- | |
− | + | ! colspan="3" | Execution Units | |
− | + | |- | |
− | + | ! Execution Unit !! # of Units !! Instructions | |
− | + | |- | |
− | + | | ALU || 4 || add, and, cmp, or, test, xor, movzx, movsx, mov, (v)movdqu, (v)movdqa, (v)movap*, (v)movup* | |
− | + | |- | |
− | + | | DIV || 1 || divp*, divs*, vdiv*, sqrt*, vsqrt*, rcp*, vrcp*, rsqrt*, idiv | |
− | + | |- | |
− | {{ | + | | Shift || 2 || sal, shl, rol, adc, sarx, adcx, adox, etc... |
+ | |- | ||
+ | | Shuffle || 1 || (v)shufp*, vperm*, (v)pack*, (v)unpck*, (v)punpck*, (v)pshuf*, (v)pslldq, (v)alignr, (v)pmovzx*, vbroadcast*, (v)pslldq, (v)psrldq, (v)pblendw | ||
+ | |- | ||
+ | | Slow Int || 1 || mul, imul, bsr, rcl, shld, mulx, pdep, etc... | ||
+ | |- | ||
+ | | Bit Manipulation || 2 || andn, bextr, blsi, blsmsk, bzhi, etc | ||
+ | |- | ||
+ | | FP Mov || 1 || (v)movsd/ss, (v)movd gpr | ||
+ | |- | ||
+ | | SIMD Misc || 1 || STTNI, (v)pclmulqdq, (v)psadw, vector shift count in xmm | ||
+ | |- | ||
+ | | Vec ALU || 3 || (v)pand, (v)por, (v)pxor, (v)movq, (v)movq, (v)movap*, (v)movup*, (v)andp*, (v)orp*, (v)paddb/w/d/q, (v)blendv*, (v)blendp*, (v)pblendd | ||
+ | |- | ||
+ | | Vec Shift || 2 || (v)psllv*, (v)psrlv*, vector shift count in imm8 | ||
+ | |- | ||
+ | | Vec Add || 2 || (v)addp*, (v)cmpp*, (v)max*, (v)min*, (v)padds*, (v)paddus*, (v)psign, (v)pabs, (v)pavgb, (v)pcmpeq*, (v)pmax, (v)cvtps2dq, (v)cvtdq2ps, (v)cvtsd2si, (v)cvtss2si | ||
+ | |- | ||
+ | | Vec Mul || 2 || (v)mul*, (v)pmul*, (v)pmadd* | ||
+ | |- | ||
+ | |colspan="3" | This table was taken verbatim from the Intel manual. Execution unit mapping to {{x86|MMX|MMX instructions}} are not included. | ||
+ | |} | ||
== Graphics == | == Graphics == | ||
{{main|intel/microarchitectures/gen9.5|l1=Gen9.5}} | {{main|intel/microarchitectures/gen9.5|l1=Gen9.5}} | ||
− | Support for three displays via [[HDMI]] 1.4<ref group=graphics>Note that while there is no native HDMI 2.0 support, Intel did provide somewhat of an awkward solution using an [[LSPCON]] ([[Level Shifter]]/[[Protocol Converter]]) to drive DP to HDMI 1.4 signal + convert HDMI 1.4 to HDMI 2.0. One such solution is the MegaChips MCDP2800.</ref>, [[DisplayPort]] (DP) 1.2, | + | Support for three displays via [[HDMI]] 1.4<ref group=graphics>Note that while there is no native HDMI 2.0 support, Intel did provide somewhat of an awkward solution using an [[LSPCON]] ([[Level Shifter]]/[[Protocol Converter]]) to drive DP to HDMI 1.4 signal + convert HDMI 1.4 to HDMI 2.0. One such solution is the MegaChips MCDP2800.</ref>, [[DisplayPort]] (DP) 1.2, an [[Embedded DisplayPort]] (eDP) 1.4 interfaces. Kaby Lake's biggest enhancement is the addition of native [[fixed function]] HEVC/VP9 decoding for 4K playback at 60fps (10-bit) as well as [[fixed function]] HEVC/VP9 encoding for 4K (8-bit). |
{| class="wikitable tc2 tc3" | {| class="wikitable tc2 tc3" | ||
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| Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux | | Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux | ||
|- | |- | ||
− | | {{intel|HD Graphics 610}} || 12 || GT1 || {{intel|Kaby Lake S|S}}, {{intel|Kaby Lake U|U}} || - || rowspan="7" colspan="2" style="text-align: center;" | '''1.0''' || rowspan="7" style="text-align: center;" | '''12''' || rowspan="7" style="text-align: center;" | '''N/A''' || rowspan="7" style="text-align: center;" | '''5.1''' || rowspan="7" style="text-align: center;" | '''4. | + | | {{intel|HD Graphics 610}} || 12 || GT1 || {{intel|Kaby Lake S|S}}, {{intel|Kaby Lake U|U}} || - || rowspan="7" colspan="2" style="text-align: center;" | '''1.0''' || rowspan="7" style="text-align: center;" | '''12''' || rowspan="7" style="text-align: center;" | '''N/A''' || rowspan="7" style="text-align: center;" | '''5.1''' || rowspan="7" style="text-align: center;" | '''4.4''' || rowspan="7" style="text-align: center;" | '''4.5''' || rowspan="7" style="text-align: center;" colspan="1" | '''2.1''' || style="text-align: center;" rowspan="7" | '''2.0''' |
|- | |- | ||
| {{intel|HD Graphics 615}} || 24 || GT2|| {{intel|Kaby Lake Y|Y}} || - | | {{intel|HD Graphics 615}} || 24 || GT2|| {{intel|Kaby Lake Y|Y}} || - | ||
|- | |- | ||
− | | {{intel|HD Graphics 620}} || 24 || GT2 || {{intel|Kaby Lake U|U | + | | {{intel|HD Graphics 620}} || 24 || GT2 || {{intel|Kaby Lake U|U}} || - |
|- | |- | ||
| {{intel|HD Graphics 630}} || 24 || GT2 || {{intel|Kaby Lake S|S}}, {{intel|Kaby Lake H|H}} || - | | {{intel|HD Graphics 630}} || 24 || GT2 || {{intel|Kaby Lake S|S}}, {{intel|Kaby Lake H|H}} || - | ||
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! !! Core !! Socket !! Permanent !! Platform !! Chipset !! Bus | ! !! Core !! Socket !! Permanent !! Platform !! Chipset !! Bus | ||
|- | |- | ||
− | | [[File:kaby lake y (back).png|100px|link=intel/cores/kaby_lake_y]] || {{intel|Kaby Lake Y|l=core}} || {{intel|BGA-1515}} || Yes || 1-chip || rowspan=" | + | | [[File:kaby lake y (back).png|100px|link=intel/cores/kaby_lake_y]] || {{intel|Kaby Lake Y|l=core}} || {{intel|BGA-1515}} || Yes || 1-chip || rowspan="2" | N/A || rowspan="2" | OPI |
|- | |- | ||
− | | [[File:kaby lake u (back; standard).png|100px|link=intel/cores/kaby_lake_u]] || {{intel|Kaby Lake U|l=core}} | | + | | [[File:kaby lake u (back; standard).png|100px|link=intel/cores/kaby_lake_u]] || {{intel|Kaby Lake U|l=core}} || {{intel|BGA-1356}} || Yes || 1-chip |
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| [[File:kaby lake h (back).png|100px|link=intel/cores/kaby_lake_h]] || {{intel|Kaby Lake H|l=core}} || {{intel|BGA-1440}} || Yes || 2-chip || rowspan="2" | {{intel|Sunrise Point}}<ref group="c">Requires a firmware update in order to work with Kaby Lake chips</ref><br>{{intel|Union Point}} || rowspan="4" | [[DMI 3.0]] | | [[File:kaby lake h (back).png|100px|link=intel/cores/kaby_lake_h]] || {{intel|Kaby Lake H|l=core}} || {{intel|BGA-1440}} || Yes || 2-chip || rowspan="2" | {{intel|Sunrise Point}}<ref group="c">Requires a firmware update in order to work with Kaby Lake chips</ref><br>{{intel|Union Point}} || rowspan="4" | [[DMI 3.0]] | ||
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| {{intel|Kaby Lake DT|l=core}} || {{intel|LGA-1151}} || No || 2-chip || Xeon {{intel|Sunrise Point}}<br>Xeon {{intel|Union Point}} | | {{intel|Kaby Lake DT|l=core}} || {{intel|LGA-1151}} || No || 2-chip || Xeon {{intel|Sunrise Point}}<br>Xeon {{intel|Union Point}} | ||
|- | |- | ||
− | | | + | | || {{intel|Kaby Lake X|l=core}} || {{intel|LGA-2066}} || No || 2-chip || {{intel|Lewisburg}} |
|} | |} | ||
<references group="c" /> | <references group="c" /> | ||
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== Clock domains == | == Clock domains == | ||
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=== Overclocking === | === Overclocking === | ||
See {{intel|Skylake#Overclocking|Skylake §Overclocking|l=arch}}. | See {{intel|Skylake#Overclocking|Skylake §Overclocking|l=arch}}. | ||
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== Die == | == Die == | ||
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<div style="float: left; margin: 10px;">[[File:kaby lake 4c sa.png|150px]]</div> | <div style="float: left; margin: 10px;">[[File:kaby lake 4c sa.png|150px]]</div> | ||
<div style="float: left; margin: 10px;">[[File:kaby lake 4c sa (annotated).png|150px]]</div> | <div style="float: left; margin: 10px;">[[File:kaby lake 4c sa (annotated).png|150px]]</div> | ||
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</div> | </div> | ||
</div> | </div> | ||
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* [[14 nm process|14 nm+ process]] | * [[14 nm process|14 nm+ process]] | ||
* 11 metal layers | * 11 metal layers | ||
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* 4 CPU cores + 24 GPU EUs | * 4 CPU cores + 24 GPU EUs | ||
− | : [[File:kaby lake (quad core).png | + | : [[File:kaby lake (quad core).png|650px]] |
: [[File:kaby lake (quad core) (annotated).png|650px]] | : [[File:kaby lake (quad core) (annotated).png|650px]] | ||
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== All Kaby Lake Chips == | == All Kaby Lake Chips == | ||
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<tr class="comptable-header"><th class="unsortable">Model</th><th>Launched</th><th data-sort-type="currency">Price</th><th>Family</th><th>Platform</th><th>Core</th><th data-sort-type="number">Cores</th><th data-sort-type="number">Threads</th><th data-sort-type="number">L3$</th><th data-sort-type="number">L4$</th><th data-sort-type="number">TDP</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th data-sort-type="number">Max Mem</th><th>Name</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th>[[ECC]]</th><th>{{intel|turbo boost|TBT}}</th><th>HT</th><th>AVX</th><th>AVX2</th><th>TXT</th><th>TSX</th><th>vPro</th><th>VT-d</th></tr> | <tr class="comptable-header"><th class="unsortable">Model</th><th>Launched</th><th data-sort-type="currency">Price</th><th>Family</th><th>Platform</th><th>Core</th><th data-sort-type="number">Cores</th><th data-sort-type="number">Threads</th><th data-sort-type="number">L3$</th><th data-sort-type="number">L4$</th><th data-sort-type="number">TDP</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th data-sort-type="number">Max Mem</th><th>Name</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th>[[ECC]]</th><th>{{intel|turbo boost|TBT}}</th><th>HT</th><th>AVX</th><th>AVX2</th><th>TXT</th><th>TSX</th><th>vPro</th><th>VT-d</th></tr> | ||
<tr class="comptable-header comptable-header-sep"><th> </th><th colspan="25">[[Uniprocessors]]</th></tr> | <tr class="comptable-header comptable-header-sep"><th> </th><th colspan="25">[[Uniprocessors]]</th></tr> | ||
− | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Kaby Lake]] [[max cpu count::1 | + | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Kaby Lake]] [[max cpu count::1]] |
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|?full page name | |?full page name | ||
|?model number | |?model number | ||
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== Documents == | == Documents == | ||
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* [[:File:7th-gen-intel-core-january-product-brief.pdf|7th gen intel core & Intel Xeon processor briefing]] | * [[:File:7th-gen-intel-core-january-product-brief.pdf|7th gen intel core & Intel Xeon processor briefing]] | ||
* [[:File:7th Generation Intel® Core™ Processor Product Brief.pdf|7th Generation Intel Core Processor Product Brief]] | * [[:File:7th Generation Intel® Core™ Processor Product Brief.pdf|7th Generation Intel Core Processor Product Brief]] | ||
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* [[:File:7th-generation-core-processor-deskop-iot-platform-brief.pdf|7th Generation Intel Core Processor-Based Platforms for Internet of Things (IoT) Solutions Platform brief]] | * [[:File:7th-generation-core-processor-deskop-iot-platform-brief.pdf|7th Generation Intel Core Processor-Based Platforms for Internet of Things (IoT) Solutions Platform brief]] | ||
* [[:File:how-to-watch-4k-uhd-premium-content-with-your-pc.pdf|HOW TO WATCH 4K ULTRA HD (UHD) PREMIUM CONTENT WITH YOUR PC]] | * [[:File:how-to-watch-4k-uhd-premium-content-with-your-pc.pdf|HOW TO WATCH 4K ULTRA HD (UHD) PREMIUM CONTENT WITH YOUR PC]] | ||
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− | == | + | == References == |
* Intel Developer Forum 2015, San Francisco, August 18-20, 2015 | * Intel Developer Forum 2015, San Francisco, August 18-20, 2015 | ||
* Intel Technology and Manufacturing Day, March 28, 2017 | * Intel Technology and Manufacturing Day, March 28, 2017 | ||
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== Artwork == | == Artwork == | ||
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File:7th-gen-wafer.jpg|7th gen core silicon wafers | File:7th-gen-wafer.jpg|7th gen core silicon wafers | ||
</gallery> | </gallery> | ||
+ | |||
+ | == External Links == | ||
+ | * [https://www.youtube.com/watch?v=3zoD3_ZZeaw Kaby Lake – All CPUs Benchmarks ROUNDUP] | ||
== See also == | == See also == | ||
* {{amd|microarchitectures/zen|AMD's Zen}} | * {{amd|microarchitectures/zen|AMD's Zen}} |
Facts about "Kaby Lake - Microarchitectures - Intel"
codename | Kaby Lake + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | August 30, 2016 + |
full page name | intel/microarchitectures/kaby lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Kaby Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |