From WikiChip
Editing intel/microarchitectures/ice lake (server)
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 5: | Line 5: | ||
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
− | |introduction= | + | |introduction=Abril, 2021 |
− | |process=10 nm | + | |process=10 nm |
|cores=8 | |cores=8 | ||
|cores 2=10 | |cores 2=10 | ||
Line 41: | Line 41: | ||
|core name=Ice Lake SP | |core name=Ice Lake SP | ||
|core name 2=Ice Lake X | |core name 2=Ice Lake X | ||
− | |predecessor= | + | |predecessor=Cooper Lake |
− | |predecessor link=intel/microarchitectures/ | + | |predecessor link=intel/microarchitectures/cooper lake |
|successor=Sapphire Rapids | |successor=Sapphire Rapids | ||
|successor link=intel/microarchitectures/sapphire rapids | |successor link=intel/microarchitectures/sapphire rapids | ||
− | |contemporary | + | |contemporary=Ice Lake (client) |
− | + | |contemporary link=intel/microarchitectures/ice_lake_(client) | |
− | |||
− | |contemporary | ||
}} | }} | ||
'''Ice Lake''' ('''ICL''', '''ICX''') '''Server Configuration''' is [[Intel]]'s successor to {{\\|Cascade Lake}}, a [[10 nm]] [[microarchitecture]] for enthusiasts and servers. | '''Ice Lake''' ('''ICL''', '''ICX''') '''Server Configuration''' is [[Intel]]'s successor to {{\\|Cascade Lake}}, a [[10 nm]] [[microarchitecture]] for enthusiasts and servers. | ||
Line 95: | Line 93: | ||
| colspan="4" | Family 6 Model ? | | colspan="4" | Family 6 Model ? | ||
|- | |- | ||
− | | rowspan="2" | | + | | rowspan="2" | ? || 0 || 0x6 || ? || ? |
|- | |- | ||
− | | colspan="4" | Family 6 Model | + | | colspan="4" | Family 6 Model ? |
|} | |} | ||
Facts about "Ice Lake (server) - Microarchitectures - Intel"
codename | Ice Lake (server) + |
core count | 8 +, 10 +, 12 +, 16 +, 18 +, 20 +, 24 +, 26 +, 28 +, 32 +, 36 +, 38 + and 40 + |
designer | Intel + |
first launched | April 2021 + |
full page name | intel/microarchitectures/ice lake (server) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Ice Lake (server) + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |