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{{microarchitecture | {{microarchitecture | ||
|atype=CPU | |atype=CPU | ||
− | |name=Ice Lake | + | |name=Ice Lake |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
− | |introduction= | + | |introduction=2019 |
− | |process=10 nm | + | |process=10 nm |
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|isa=x86-64 | |isa=x86-64 | ||
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|core name=Ice Lake SP | |core name=Ice Lake SP | ||
|core name 2=Ice Lake X | |core name 2=Ice Lake X | ||
|predecessor=Cascade Lake | |predecessor=Cascade Lake | ||
− | |predecessor link=intel/microarchitectures/ | + | |predecessor link=intel/microarchitectures/cannon lake |
|successor=Sapphire Rapids | |successor=Sapphire Rapids | ||
|successor link=intel/microarchitectures/sapphire rapids | |successor link=intel/microarchitectures/sapphire rapids | ||
− | |contemporary | + | |contemporary=Ice Lake (client) |
− | + | |contemporary link=intel/microarchitectures/ice_lake_(client) | |
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− | |contemporary | ||
}} | }} | ||
− | '''Ice Lake''' ('''ICL | + | '''Ice Lake''' ('''ICL''') '''Server Configuration''' is [[Intel]]'s successor to {{\\|Cascade Lake}}, a [[10 nm]] [[microarchitecture]] for enthusiasts and servers. |
== Codenames == | == Codenames == | ||
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| {{intel|Ice Lake SP|l=core}} || ICL-SP || Server Scalable Processors | | {{intel|Ice Lake SP|l=core}} || ICL-SP || Server Scalable Processors | ||
|} | |} | ||
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== Process Technology== | == Process Technology== | ||
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! Compiler !! Arch-Specific || Arch-Favorable | ! Compiler !! Arch-Specific || Arch-Favorable | ||
|- | |- | ||
− | | [[ICC]] || <code>-march=icelake | + | | [[ICC]] || <code>-march=icelake</code> || <code>-mtune=icelake</code> |
|- | |- | ||
− | | [[GCC]] || <code>-march=icelake | + | | [[GCC]] || <code>-march=icelake</code> || <code>-mtune=icelake</code> |
|- | |- | ||
− | | [[LLVM]] || <code>-march=icelake | + | | [[LLVM]] || <code>-march=icelake</code> || <code>-mtune=icelake</code> |
|- | |- | ||
− | | [[Visual Studio]] || <code>/ | + | | [[Visual Studio]] || <code>/?</code> || <code>/tune:?</code> |
|} | |} | ||
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| colspan="4" | Family 6 Model ? | | colspan="4" | Family 6 Model ? | ||
|- | |- | ||
− | | rowspan="2" | | + | | rowspan="2" | ? || 0 || 0x6 || ? || ? |
|- | |- | ||
− | | colspan="4" | Family 6 Model | + | | colspan="4" | Family 6 Model ? |
|} | |} | ||
== Architecture == | == Architecture == | ||
+ | Not much is known about Ice Lake's architecture. | ||
=== Key changes from {{\\|Cascade Lake}}=== | === Key changes from {{\\|Cascade Lake}}=== | ||
+ | {{future information}} | ||
+ | |||
* Enhanced "10nm+" (from [[14 nm]]) | * Enhanced "10nm+" (from [[14 nm]]) | ||
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====New instructions ==== | ====New instructions ==== | ||
− | Ice Lake introduced a number of {{x86|extensions|new instructions}} | + | Ice Lake introduced a number of {{x86|extensions|new instructions}}: |
+ | |||
+ | * {{x86|CLWB|<code>CLWB</code>}} - Force cache line write-back without flush | ||
+ | * {{x86|RDPID|<code>RDPID</code>}} - Read Processor ID | ||
+ | * Additional {{x86|AVX-512}} extensions: | ||
+ | ** {{x86|AVX512VPOPCNTDQ|<code>AVX512VPOPCNTDQ</code>}} - AVX-512 Vector Population Count Doubleword and Quadword | ||
+ | ** {{x86|AVX512VNNI|<code>AVX512VNNI</code>}} - AVX-512 Vector Neural Network Instructions | ||
+ | ** {{x86|AVX512GFNI|<code>AVX512GFNI</code>}} - AVX-512 Galois Field New Instructions | ||
+ | ** {{x86|AVX512VAES|<code>AVX512VAES</code>}} - AVX-512 Vector AES | ||
+ | ** {{x86|AVX512VBMI2|<code>AVX512VBMI2</code>}} - AVX-512 Vector Bit Manipulation, Version 2 | ||
+ | ** {{x86|AVX512BITALG|<code>AVX512BITALG</code>}} - AVX-512 Bit Algorithms | ||
+ | ** {{x86|AVX512VPCLMULQDQ|<code>AVX512VPCLMULQDQ</code>}} - AVX-512 Vector Vector Carry-less Multiply | ||
+ | * {{x86|TME|<code>TME</code>}} - Total Memory Encryption | ||
+ | * Fast Short REP MOV | ||
== All Ice Lake Chips == | == All Ice Lake Chips == |
Facts about "Ice Lake (server) - Microarchitectures - Intel"
codename | Ice Lake (server) + |
core count | 8 +, 10 +, 12 +, 16 +, 18 +, 20 +, 24 +, 26 +, 28 +, 32 +, 36 +, 38 + and 40 + |
designer | Intel + |
first launched | April 2021 + |
full page name | intel/microarchitectures/ice lake (server) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Ice Lake (server) + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |