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Latest revision | Your text | ||
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*** Per core | *** Per core | ||
** L2 Cache: | ** L2 Cache: | ||
− | *** | + | *** 4 MiB 16-way set associative, 64 B line size |
*** Per 2 cores | *** Per 2 cores | ||
*** 32B/cycle, 19 cycle latency | *** 32B/cycle, 19 cycle latency |
Facts about "Goldmont Plus - Microarchitectures - Intel"
codename | Goldmont Plus + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | December 11, 2017 + |
full page name | intel/microarchitectures/goldmont plus + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Goldmont Plus + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |