From WikiChip
Editing intel/microarchitectures/goldmont plus
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 26: | Line 26: | ||
|extension 11=PCLMUL | |extension 11=PCLMUL | ||
|extension 12=RDRND | |extension 12=RDRND | ||
− | |extension 13 | + | |extension 13=SHA |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|l1i=32 KiB | |l1i=32 KiB | ||
|l1i per=Core | |l1i per=Core | ||
Line 44: | Line 37: | ||
|l2 desc=16-way set associative | |l2 desc=16-way set associative | ||
|core name=Gemini Lake | |core name=Gemini Lake | ||
− | |||
|predecessor=Goldmont | |predecessor=Goldmont | ||
|predecessor link=intel/microarchitectures/goldmont | |predecessor link=intel/microarchitectures/goldmont | ||
− | |||
− | |||
}} | }} | ||
− | '''Goldmont Plus''' ( | + | '''Goldmont Plus''' ('''GLP''') is [[Intel]]'s [[14 nm]] [[microarchitecture]] of [[system on chip]]s for the ultra-low power (ULP) devices serving as a successor to {{\\|Goldmont}}. Goldmont Plus-based processors and SoCs are part of the {{intel|Atom}}, {{intel|Pentium Silver}}, and {{intel|Celeron}} families. |
== Codenames == | == Codenames == | ||
Line 58: | Line 48: | ||
|- | |- | ||
| {{intel|Gemini Lake}} || GLK || Low-power PCs, tablets, and embedded devices | | {{intel|Gemini Lake}} || GLK || Low-power PCs, tablets, and embedded devices | ||
− | |||
− | |||
|} | |} | ||
Line 77: | Line 65: | ||
== Release Dates == | == Release Dates == | ||
− | Goldmont Plus processors were launched on December 11 | + | Goldmont Plus processors were launched on December 11 2017 for desktop, mobile and embedded devices. Server-based parts are expected to be introduced in 2018. |
== Technology == | == Technology == | ||
− | Goldmont Plus, like its predecessor | + | Goldmont Plus, like its predecessor is manufactured on Intel's original [[14 nm process]] (as opposed to 14nm+ or 14nm++). |
== Compiler support == | == Compiler support == | ||
Line 101: | Line 89: | ||
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model | ||
|- | |- | ||
− | | rowspan="2" | {{intel|Gemini Lake|l=core}} || 0 || | + | | rowspan="2" | {{intel|Gemini Lake|l=core}} || 0 || ? || ? || ? |
|- | |- | ||
− | | colspan="4" | Family 6 Model | + | | colspan="4" | Family 6 Model ? |
|} | |} | ||
Line 118: | Line 106: | ||
** Larger ROB | ** Larger ROB | ||
** Execution Units | ** Execution Units | ||
− | |||
− | |||
− | |||
− | |||
** Wider integer execution unit | ** Wider integer execution unit | ||
** New dedicated JEU port | ** New dedicated JEU port | ||
Line 169: | Line 153: | ||
*** 2 MiB 16-way set associative, 64 B line size | *** 2 MiB 16-way set associative, 64 B line size | ||
*** Per 2 cores | *** Per 2 cores | ||
− | |||
** L3 Cache: | ** L3 Cache: | ||
*** No level 3 cache | *** No level 3 cache |
Facts about "Goldmont Plus - Microarchitectures - Intel"
codename | Goldmont Plus + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | December 11, 2017 + |
full page name | intel/microarchitectures/goldmont plus + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Goldmont Plus + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |