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|stages min=12 | |stages min=12 | ||
|stages max=14 | |stages max=14 | ||
− | |isa=x86-64 | + | |isa=IA-32 |
+ | |isa 2=x86-64 | ||
|extension=MOVBE | |extension=MOVBE | ||
|extension 2=MMX | |extension 2=MMX | ||
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|extension 11=PCLMUL | |extension 11=PCLMUL | ||
|extension 12=RDRND | |extension 12=RDRND | ||
− | |extension 13 | + | |extension 13=SHA |
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|l1i=32 KiB | |l1i=32 KiB | ||
|l1i per=Core | |l1i per=Core | ||
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== Architecture == | == Architecture == | ||
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=== Key changes from {{intel|Airmont}} === | === Key changes from {{intel|Airmont}} === | ||
* Pipeline | * Pipeline | ||
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** {{intel|HD Graphics 400}} '''→''' {{intel|HD Graphics 500}} (12 Execution Units, no change) | ** {{intel|HD Graphics 400}} '''→''' {{intel|HD Graphics 500}} (12 Execution Units, no change) | ||
** {{intel|HD Graphics 405}} '''→''' {{intel|HD Graphics 505}} (18 Execution Units, up from 16) | ** {{intel|HD Graphics 405}} '''→''' {{intel|HD Graphics 505}} (18 Execution Units, up from 16) | ||
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=== Block Diagram === | === Block Diagram === | ||
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*** 1 MiB 16-way set associative, 64 B line size | *** 1 MiB 16-way set associative, 64 B line size | ||
*** Per 2 cores | *** Per 2 cores | ||
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** L3 Cache: | ** L3 Cache: | ||
*** No level 3 cache | *** No level 3 cache |
Facts about "Goldmont - Microarchitectures - Intel"
codename | Goldmont + |
core count | 2 +, 4 +, 8 +, 12 + and 16 + |
designer | Intel + |
first launched | August 30, 2016 + |
full page name | intel/microarchitectures/goldmont + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Goldmont + |
pipeline stages (max) | 14 + |
pipeline stages (min) | 12 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |