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{{intel title|Goldmont|arch}} | {{intel title|Goldmont|arch}} | ||
{{microarchitecture | {{microarchitecture | ||
− | + | | name = Goldmont | |
− | |name=Goldmont | + | | designer = Intel |
− | |designer=Intel | + | | manufacturer = Intel |
− | |manufacturer=Intel | + | | introduction = August 30, 2016 |
− | |introduction=August 30, 2016 | + | | phase-out = |
− | |process=14 nm | + | | process = 14 nm |
− | |cores=2 | + | | cores = 2 |
− | |cores 2=4 | + | | cores 2 = 4 |
− | |cores 3=8 | + | | cores 3 = 8 |
− | | | + | |
− | | | + | | pipeline = Yes |
− | | | + | | type = Superscalar |
− | |speculative=Yes | + | | OoOE = Yes |
− | |renaming=Yes | + | | speculative = Yes |
− | |stages min=12 | + | | renaming = Yes |
− | |stages max=14 | + | | isa = IA-32 |
− | | | + | | isa 2 = x86-64 |
− | |extension=MOVBE | + | | stages min = 12 |
− | |extension 2=MMX | + | | stages max = 14 |
− | |extension 3=SSE | + | | issues = 3 |
− | |extension 4=SSE2 | + | |
− | |extension 5=SSE3 | + | | inst = Yes |
− | |extension 6=SSSE3 | + | | feature = |
− | |extension 7=SSE4.1 | + | | extension = MOVBE |
− | |extension 8=SSE4.2 | + | | extension 2 = MMX |
− | |extension 9=POPCNT | + | | extension 3 = SSE |
− | |extension 10=AES | + | | extension 4 = SSE2 |
− | |extension 11=PCLMUL | + | | extension 5 = SSE3 |
− | |extension 12=RDRND | + | | extension 6 = SSSE3 |
− | + | | extension 7 = SSE4.1 | |
− | | | + | | extension 8 = SSE4.2 |
− | + | | extension 9 = POPCNT | |
− | + | | extension 10 = AES | |
− | |l1i=32 KiB | + | | extension 11 = PCLMUL |
− | |l1i per=Core | + | | extension 12 = RDRND |
− | |l1i desc=8-way set associative | + | |
− | |l1d=24 KiB | + | | cache = Yes |
− | |l1d per=Core | + | | l1i = 32 KiB |
− | |l1d desc=6-way set associative | + | | l1i per = Core |
− | |l2=1 | + | | l1i desc = 8-way set associative |
− | |l2 per=2 Cores | + | | l1d = 24 KiB |
− | |l2 desc=16-way set associative | + | | l1d per = Core |
− | |core name=Apollo Lake | + | | l1d desc = 6-way set associative |
− | |core name 2= | + | | l2 = 1 MiB |
− | |predecessor=Airmont | + | | l2 per = 2 Cores |
− | |predecessor link=intel/microarchitectures/airmont | + | | l2 desc = 16-way set associative |
− | |successor= | + | |
− | |successor link= | + | | core names = Yes |
+ | | core name = Apollo Lake | ||
+ | | core name 2 = | ||
+ | | core name N = | ||
+ | |||
+ | | succession = Yes | ||
+ | | predecessor = Airmont | ||
+ | | predecessor link = intel/microarchitectures/airmont | ||
+ | | successor = | ||
+ | | successor link = | ||
}} | }} | ||
− | '''Goldmont''' | + | '''Goldmont''' is [[Intel]]'s [[14 nm]] [[microarchitecture]] of [[system on chip]]s for the ultra-low power (ULP) devices. Goldmont-based processors and SoCs are part of the {{intel|Atom}}, {{intel|Pentium (2009)|Pentium}}, and {{intel|Celeron}} families. Goldmont superseded {{intel|Airmont}} in August of 2016. With Goldmont, Intel stopped targeting smartphones altogether, cancelling the related cores and SKUs. |
[[File:Atom E3900 SoC Front.png|right|thumb|250px|Intel Atom E3900 SoC series]] | [[File:Atom E3900 SoC Front.png|right|thumb|250px|Intel Atom E3900 SoC series]] | ||
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! Platform !! Core !! Target | ! Platform !! Core !! Target | ||
|- | |- | ||
− | + | | {{intel|Apollo Lake}} || {{intel|Apollo Lake}} || Tablets, Entry-level PCs | |
− | + | |- style="text-decoration: line-through;" | |
− | + | | {{intel|Willow Trail}} || {{intel|Willow Trail}} || Lightweight Tablets & high-end smartphone | |
− | |- | ||
− | |||
|- style="text-decoration: line-through;" | |- style="text-decoration: line-through;" | ||
− | | {{intel|Morganfield | + | | {{intel|Morganfield}} || {{intel|Broxton}} || Smartphone |
|} | |} | ||
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== Architecture == | == Architecture == | ||
− | + | ||
=== Key changes from {{intel|Airmont}} === | === Key changes from {{intel|Airmont}} === | ||
* Pipeline | * Pipeline | ||
** Compared to Airmont, Goldmont is a 3-issue core. | ** Compared to Airmont, Goldmont is a 3-issue core. | ||
− | ** NOPs, MOVs and many ALU operations have 3 op/cycle throughput for 16, 32 and 64-bit registers. (8-bit ALU ops throughput is 2, 1.5 or 1 op per cycle). | + | ** Throughput |
− | ** ADC, SBB have 0.5 op/cycle throughput, unchanged from Airmont. | + | *** NOPs, MOVs and many ALU operations have 3 op/cycle throughput for 16, 32 and 64-bit registers. (8-bit ALU ops throughput is 2, 1.5 or 1 op per cycle). |
− | ** INC, DEC, BTx, shift ops are not faster than on Airmont, 8-bit shifts are slightly slower (0.66 op/cycle instead of 1). | + | *** ADC, SBB have 0.5 op/cycle throughput, unchanged from Airmont. |
− | ** Rotate-through-carry (RCL, RCR) throughput continues to be slow and is slightly slower (used to be ~10 cycles per op, now ~12). | + | *** INC, DEC, BTx, shift ops are not faster than on Airmont, 8-bit shifts are slightly slower (0.66 op/cycle instead of 1). |
− | ** 16- and 64-bit shift-double (SHLD, SHRD) throughput continues to be slow and is slightly slower (used to be ~10 cycles per op, now ~14) than on Airmont. (32-bit SHLD, SHRD are fast: 2-4 cycles). | + | *** Rotate-through-carry (RCL, RCR) throughput continues to be slow and is slightly slower (used to be ~10 cycles per op, now ~12). |
− | ** Variable shifts and rotates (SHL r32, CL etc) latency increased from 1 cycle to 2 cycles. | + | *** 16- and 64-bit shift-double (SHLD, SHRD) throughput continues to be slow and is slightly slower (used to be ~10 cycles per op, now ~14) than on Airmont. (32-bit SHLD, SHRD are fast: 2-4 cycles). |
− | ** Bit scan (BSF, BSR) throughput improved from 10 to 8 cycles per op. | + | *** Variable shifts and rotates (SHL r32, CL etc) latency increased from 1 cycle to 2 cycles. |
− | ** MUL throughput is better by 1 cycle (used to be 5/7 cycles for 32/64-bit mul, now 4/6). | + | *** Bit scan (BSF, BSR) throughput improved from 10 to 8 cycles per op. |
− | ** DIV is more than twice as fast as Airmont, 13 cycles for most divides, 128-bit/64-bit are ~42 cycles. | + | *** MUL throughput is better by 1 cycle (used to be 5/7 cycles for 32/64-bit mul, now 4/6). |
− | ** PUSH to POP forwarding is improved. | + | *** DIV is more than twice as fast as Airmont, 13 cycles for most divides, 128-bit/64-bit are ~42 cycles. |
− | ** REP MOVS streaming copy is twice as fast: now ~26 bytes/cycle. | + | *** PUSH to POP forwarding is improved. |
− | ** REP STOS fill is not improved: ~9 bytes/cycle. | + | *** REP MOVS streaming copy is twice as fast: now ~26 bytes/cycle. |
− | ** Some vector instructions are faster, but like on {{\\|Airmont}}, none have throughput >2 op/cycle. This includes often used ops like adds and multiplies: | + | *** REP STOS fill is not improved: ~9 bytes/cycle. |
− | *** MULPS and MULPD have 4 cycle latency and 1 op/cycle throughput (used to have L5 and T0.5). | + | *** Some vector instructions are faster, but like on {{\\|Airmont}}, none have throughput >2 op/cycle. This includes often used ops like adds and multiplies: |
− | *** ADDPD has 3 cycle latency and 1 op/cycle throughput (used to have L4 and T0.5). | + | **** MULPS and MULPD have 4 cycle latency and 1 op/cycle throughput (used to have L5 and T0.5). |
− | ** CRC32 instruction throughput improved from 6 cycles/op to 1 cycle/op, latency is halved from 6 to 3. | + | **** ADDPD has 3 cycle latency and 1 op/cycle throughput (used to have L4 and T0.5). |
+ | *** CRC32 instruction throughput improved from 6 cycles/op to 1 cycle/op, latency is halved from 6 to 3. | ||
* Gen 9 GPUs | * Gen 9 GPUs | ||
** {{intel|HD Graphics 400}} '''→''' {{intel|HD Graphics 500}} (12 Execution Units, no change) | ** {{intel|HD Graphics 400}} '''→''' {{intel|HD Graphics 500}} (12 Execution Units, no change) | ||
** {{intel|HD Graphics 405}} '''→''' {{intel|HD Graphics 505}} (18 Execution Units, up from 16) | ** {{intel|HD Graphics 405}} '''→''' {{intel|HD Graphics 505}} (18 Execution Units, up from 16) | ||
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=== Block Diagram === | === Block Diagram === | ||
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*** 1 MiB 16-way set associative, 64 B line size | *** 1 MiB 16-way set associative, 64 B line size | ||
*** Per 2 cores | *** Per 2 cores | ||
− | |||
** L3 Cache: | ** L3 Cache: | ||
*** No level 3 cache | *** No level 3 cache |
Facts about "Goldmont - Microarchitectures - Intel"
codename | Goldmont + |
core count | 2 +, 4 +, 8 +, 12 + and 16 + |
designer | Intel + |
first launched | August 30, 2016 + |
full page name | intel/microarchitectures/goldmont + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Goldmont + |
pipeline stages (max) | 14 + |
pipeline stages (min) | 12 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |