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− | {{intel title| | + | {{intel title|Cannonlake|arch}} |
{{microarchitecture | {{microarchitecture | ||
− | |atype=CPU | + | | atype = CPU |
− | |name= | + | | name = Cannonlake |
− | |designer=Intel | + | | designer = Intel |
− | |manufacturer=Intel | + | | manufacturer = Intel |
− | |introduction= | + | | introduction = 2017 |
− | | | + | | phase-out = |
− | + | | process = 10 nm | |
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− | + | | core names = Yes | |
+ | | core name = Cannonlake Y | ||
+ | | core name 2 = Cannonlake U | ||
+ | | core name 3 = | ||
+ | | core name 4 = | ||
+ | | core name 5 = | ||
+ | | core name 6 = | ||
− | == | + | | succession = Yes |
− | + | | predecessor = Kaby Lake | |
− | | | + | | predecessor link = intel/microarchitectures/kaby lake |
− | + | | successor = Icelake | |
− | + | | successor link = intel/microarchitectures/icelake | |
− | + | }} | |
− | |} | + | '''Cannonlake''' ('''CNL''') (formerly '''Skymont''') is a planned [[microarchitecture]] by [[Intel]] as a successor to {{\\|Kaby Lake}}. Cannonlake is expected to be fabricated using a [[10 nm process]] and is set to be introduced in the fourth quarter of [[2017]]. Cannonlake is the "Process" microarchitecture as part of Intel's {{intel|PAO}} model. |
− | + | For mobile, Cannonlake is expected to be branded as 8th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}. and {{intel|Core i7}} processors. There will be no desktop Cannonlake models. | |
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== Process Technology == | == Process Technology == | ||
− | + | Cannonlake is manufactured on Intel's [[10 nm process]] (P1274). Intel's 10 nm process is the first high-volume manufacturing process to employ [[Self-Aligned Quad Patterning]] (SAQP) (goes under the "Hyper-Scaling" marketing name). Intel's 10nm features a 0.0367 µm² [[SRAM]] bit cell. | |
[[Scaling]]: | [[Scaling]]: | ||
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{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
− | ! !! Broadwell !! | + | ! !! Broadwell !! Cannonlake !! Δ !! rowspan="8" | [[File:intel 10nm fin.png|250px]] |
|- | |- | ||
| || [[14 nm]] || [[10 nm]] || | | || [[14 nm]] || [[10 nm]] || | ||
|- | |- | ||
− | | Fin Pitch || | + | | Fin Pitch || 42 nm || 34 || 0.81x |
|- | |- | ||
− | | Fin Width || | + | | Fin Width || 8 nm || ? nm || ?x |
|- | |- | ||
− | | Fin Height || | + | | Fin Height || 42 nm || 53 nm || 1.24x |
|- | |- | ||
− | | Gate Pitch || | + | | Gate Pitch || 70 nm || 54 nm || 0.77x |
|- | |- | ||
− | | Interconnect Pitch || | + | | Interconnect Pitch || 52 nm || 36 nm || 0.69x |
|- | |- | ||
| Cell Height || 399 nm || 272 nm || 0.68x | | Cell Height || 399 nm || 272 nm || 0.68x | ||
|} | |} | ||
− | == | + | == Codenames == |
− | + | Intel cancelled Desktop Cannonlake models. | |
+ | |||
{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
− | ! | + | ! Core !! Abbrev !! Description !! Graphics !! Target |
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|- | |- | ||
− | | | + | | {{intel|Cannonlake Y|l=core}} || KBL-Y || Extremely low power || GT2 || 2-in-1s detachable, tablets, and computer sticks |
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|- | |- | ||
− | + | | {{intel|Cannonlake U|l=core}} || KBL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room | |
|- | |- | ||
− | | | + | | {{intel|Cannonlake H|l=core}} || KBL-H || High-performance Graphics || GT2/GT3 || Ultimate mobile performance, mobile workstations |
+ | |- style="text-decoration: line-through;" | ||
+ | | {{intel|Cannonlake S|l=core}} || KBL-S || Performance-optimized lifestyle || GT2/GT3 || Desktop performance to value, AiOs, and minis | ||
+ | |- style="text-decoration: line-through;" | ||
+ | | {{intel|Cannonlake DT|l=core}} || KBL-DT || Workstation || GT2 || Workstations & entry-level servers | ||
|} | |} | ||
== Architecture == | == Architecture == | ||
− | === Key changes from {{\\| | + | {{empty section}} |
+ | === Key changes from {{\\|Kaby Lake}} === | ||
* [[10 nm process]] (from [[14 nm]]) | * [[10 nm process]] (from [[14 nm]]) | ||
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* Mainstream chipset | * Mainstream chipset | ||
− | ** {{intel|Union Point|200 Series chipset|l=chipset}} → | + | ** {{intel|Union Point|200 Series chipset|l=chipset}} → 300 Series chipset |
− | + | *** Integrated Programmable (Open FW SDK) Quad-Core Audio DSP | |
− | * | + | *** Soundwire Digital Audio Interface |
− | ** | + | *** Integrated USB 3.1 (10 Gib/s) |
− | *** | + | **** Up to 6 ports |
+ | *** Integrated Intel wireless controller ([[IEEE 802.11ac]]) | ||
+ | *** Integrated SDXC 3.0 controller | ||
+ | *** Thunderbolt 3.0(Titan Ridge) with DisplayPort 1.4 support | ||
+ | *** C10 & S0ix Support for Modern Standy | ||
* {{intel|Gen9.5|l=arch}} → {{intel|Gen10|l=arch}} graphics | * {{intel|Gen9.5|l=arch}} → {{intel|Gen10|l=arch}} graphics | ||
* {{intel|Gen10|l=arch}} GPUs | * {{intel|Gen10|l=arch}} GPUs | ||
− | ** HD Graphics | + | ** {{intel|HD Graphics 610}} '''→''' {{intel|HD Graphics 710}} (24 Execution Units, 2x EUs from {{\\|Kaby Lake}}) |
− | ** HD Graphics | + | ** {{intel|HD Graphics 615}} '''→''' {{intel|HD Graphics 715}} (40 Execution Units, 1.7x EUs from {{\\|Kaby Lake}}) |
− | + | ** {{intel|HD Graphics 620}} '''→''' {{intel|HD Graphics 720}} (40 Execution Units, 1.7x EUs from {{\\|Kaby Lake}}) | |
− | * | + | ** {{intel|HD Graphics 630}} '''→''' {{intel|HD Graphics 730}} (40 Execution Units, 1.7x EUs from {{\\|Kaby Lake}}) |
− | * | + | ** {{intel|HD Graphics P630}} '''→''' {{intel|HD Graphics P730}} (40 Execution Units, 1.7x EUs from {{\\|Kaby Lake}}) |
− | + | ** {{intel|Iris Plus Graphics 640}} '''→''' {{intel|Iris Plus Graphics 740}} (unknown change) | |
− | + | ** {{intel|Iris Plus Graphics 650}} '''→''' {{intel|Iris Plus Graphics 750}} (unknown change) | |
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− | + | == All Cannonlake Chips == | |
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− | == All | ||
<!-- NOTE: | <!-- NOTE: | ||
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created and tagged accordingly. | created and tagged accordingly. | ||
− | Missing a chip? please dump its name here: | + | Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips |
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{{comp table start}} | {{comp table start}} | ||
− | <table class="comptable sortable | + | <table class="comptable sortable tc18 tc19 tc20 tc21 tc22 tc23"> |
− | + | <tr class="comptable-header"><th> </th><th colspan="23">Cannonlake Chips</th></tr> | |
− | + | <tr class="comptable-header"><th> </th><th colspan="13">Main processor</th><th colspan="3">IGP</th><th colspan="7">Major Feature Diff</th></tr> | |
− | {{#ask: [[Category:microprocessor models by intel]] [[microarchitecture:: | + | <tr class="comptable-header"><th class="unsortable">Model</th><th>Launched</th><th>Price</th><th>Family</th><th>Platform</th><th>Core</th><th>C</th><th>T</th><th>L3$</th><th>L4$</th><th>TDP</th><th>Freq</th><th>Turbo</th><th>Max Mem</th><th>Name</th><th>Freq</th><th>Turbo</th><th>{{intel|turbo boost|TBT}}</th><th>HT</th><th>AVX2</th><th>TXT</th><th>TSX</th><th>vPro</th><th>VT-d</th></tr> |
+ | <tr class="comptable-header comptable-header-sep"><th> </th><th colspan="23">[[Uniprocessors]]</th></tr> | ||
+ | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Cannonlake]] [[max cpu count::1]] | ||
|?full page name | |?full page name | ||
|?model number | |?model number | ||
+ | |?first launched | ||
|?release price | |?release price | ||
− | |? | + | |?microprocessor family |
+ | |?platform | ||
+ | |?core name | ||
|?core count | |?core count | ||
|?thread count | |?thread count | ||
+ | |?l3$ size | ||
+ | |?l4$ size | ||
|?tdp | |?tdp | ||
|?base frequency#GHz | |?base frequency#GHz | ||
|?turbo frequency (1 core)#GHz | |?turbo frequency (1 core)#GHz | ||
+ | |?max memory#GiB | ||
+ | |?integrated gpu | ||
+ | |?integrated gpu base frequency | ||
+ | |?integrated gpu max frequency | ||
+ | |?has intel turbo boost technology 2_0 | ||
+ | |?has simultaneous multithreading | ||
+ | |?has advanced vector extensions 2 | ||
+ | |?has intel trusted execution technology | ||
+ | |?has transactional synchronization extensions | ||
+ | |?has intel vpro technology | ||
+ | |?has_intel_vt-d_technology | ||
|format=template | |format=template | ||
|template=proc table 3 | |template=proc table 3 | ||
− | |userparam= | + | |searchlabel= |
+ | |sort=microprocessor family, model number | ||
+ | |order=asc,asc | ||
+ | |userparam=25:19 | ||
|mainlabel=- | |mainlabel=- | ||
+ | |limit=100 | ||
}} | }} | ||
− | {{comp table count|ask=[[Category:microprocessor models by intel]] [[microarchitecture:: | + | <tr><th> </th><th colspan="23"><span style="font-size: 20px;">No Cannonlake Chips have been released yet.</span></th></tr> |
+ | {{comp table count|ask=[[Category:microprocessor models by intel]][[instance of::microprocessor]][[microarchitecture::Cannonlake]]}} | ||
</table> | </table> | ||
{{comp table end}} | {{comp table end}} | ||
== References == | == References == | ||
− | |||
* Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017. | * Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017. | ||
== See also == | == See also == | ||
* AMD's {{amd|Zen|l=arch}} | * AMD's {{amd|Zen|l=arch}} |
Facts about "Cannon Lake - Microarchitectures - Intel"
codename | Cannon Lake + |
core count | 2 + |
designer | Intel + |
first launched | May 15, 2018 + |
full page name | intel/microarchitectures/cannon lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Cannon Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |