From WikiChip
Editing intel/microarchitectures/bonnell
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 1: | Line 1: | ||
{{intel title|Bonnell|arch}} | {{intel title|Bonnell|arch}} | ||
{{microarchitecture | {{microarchitecture | ||
− | |atype=CPU | + | | atype = CPU |
− | |name=Bonnell | + | | name = Bonnell |
− | |designer=Intel | + | | designer = Intel |
− | |manufacturer=Intel | + | | manufacturer = Intel |
− | |introduction=March 2, 2008 | + | | introduction = March 2, 2008 |
− | |phase-out=2011 | + | | phase-out = 2011 |
− | |process=45 nm | + | | process = 45 nm |
− | |cores=1 | + | | cores = 1 |
− | |cores 2=2 | + | | cores 2 = 2 |
− | |type=Superscalar | + | |
− | | | + | | pipeline = Yes |
− | |speculative= | + | | type = Superscalar |
− | |renaming=No | + | | OoOE = No |
− | |stages min=16 | + | | speculative = No |
− | |stages max=19 | + | | renaming = No |
− | | | + | | isa = x86-32 |
− | |extension=MOVBE | + | | isa 2 = x86-64 |
− | |extension 2=MMX | + | | stages min = 16 |
− | |extension 3=SSE | + | | stages max = 19 |
− | |extension 4=SSE2 | + | | issues = 2 |
− | |extension 5=SSE3 | + | |
− | |extension 6=SSSE3 | + | | inst = Yes |
− | |l1i=32 KiB | + | | feature = |
− | |l1i per=Core | + | | extension = MOVBE |
− | |l1i desc=8-way set associative | + | | extension 2 = MMX |
− | |l1d=24 KiB | + | | extension 3 = SSE |
− | |l1d per=Core | + | | extension 4 = SSE2 |
− | |l1d desc=6-way set associative | + | | extension 5 = SSE3 |
− | |l2=512 KiB | + | | extension 6 = SSSE3 |
− | |l2 per=Core | + | |
− | |l2 desc=8-way set associative | + | | cache = Yes |
− | |core name=Silverthorne | + | | l1i = 32 KiB |
− | |core name 2=Diamondville | + | | l1i per = Core |
− | |core name 3=Lincroft | + | | l1i desc = 8-way set associative |
− | |core name 4=Pineview | + | | l1d = 24 KiB |
− | |core name 5=Tunnel Creek | + | | l1d per = Core |
− | |core name 6=Stellarton | + | | l1d desc = 6-way set associative |
− | |core name 7=Sodaville | + | | l2 = 512 KiB |
− | |core name 8=Groveland | + | | l2 per = Core |
− | |successor=Saltwell | + | | l2 desc = 8-way set associative |
− | |successor link=intel/microarchitectures/saltwell | + | |
− | + | | core names = Yes | |
− | + | | core name = Silverthorne | |
− | + | | core name 2 = Diamondville | |
− | + | | core name 3 = Lincroft | |
− | + | | core name 4 = Pineview | |
− | + | | core name 5 = Tunnel Creek | |
− | + | | core name 6 = Stellarton | |
+ | | core name 7 = Sodaville | ||
+ | | core name 8 = Groveland | ||
+ | |||
+ | | succession = Yes | ||
+ | | predecessor = | ||
+ | | successor = Saltwell | ||
+ | | successor link = intel/microarchitectures/saltwell | ||
}} | }} | ||
'''Bonnell''' was a [[microarchitecture]] for [[Intel]]'s [[45 nm]] ultra-low voltage [[microprocessor]]s first introduced in 2008 for their then-new {{intel|Atom}} family. Bonnell, which was named after the highest point in [[wikipedia:Austin, Texas|Austin]] - [[wikipedia:Mount Bonnell|Mount Bonnell]], was Intel's first x86-compatible [[microarchitecture]] designed to target the ultra-low power market. | '''Bonnell''' was a [[microarchitecture]] for [[Intel]]'s [[45 nm]] ultra-low voltage [[microprocessor]]s first introduced in 2008 for their then-new {{intel|Atom}} family. Bonnell, which was named after the highest point in [[wikipedia:Austin, Texas|Austin]] - [[wikipedia:Mount Bonnell|Mount Bonnell]], was Intel's first x86-compatible [[microarchitecture]] designed to target the ultra-low power market. | ||
Line 88: | Line 95: | ||
{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
− | ! First Generation !! !! Second Generation | + | ! First Generation !! !! Second Generation |
+ | |- | ||
+ | | {{intel|Silverthorne|l=core}} || → || {{intel|Lincroft}} | ||
|- | |- | ||
− | | {{intel| | + | | {{intel|Diamondville|l=core}} || → || {{intel|Pineview}} |
|- | |- | ||
− | | | + | | || || {{intel|Tunnel Creek}} |
|- | |- | ||
− | | || || {{intel| | + | | || || {{intel|Stellarton}} |
|- | |- | ||
− | | || || {{intel| | + | | || || {{intel|Sodaville}} |
|- | |- | ||
− | | || | + | | || || {{intel|Groveland}} |
|} | |} | ||
== Brands == | == Brands == | ||
− | Intel sold | + | Intel sold bonnell-based processors under the '''{{intel|Atom}}''' brand. Additionally, manufacturers were allowed to use the '''Centrino Atom''' brand if the system consist of a bonnell-based processor, the chipset, wireless capabilities ([[WiFi]], [[3G]], [[WiMAX]]), is battery powered, and had a screen size of up to 6". |
{| class="wikitable" | {| class="wikitable" | ||
Line 149: | Line 158: | ||
|} | |} | ||
{{clear}} | {{clear}} | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
== Compiler support == | == Compiler support == | ||
Line 189: | Line 180: | ||
Performance/Power new rule: +1% performance for at most +1% power consumption. | Performance/Power new rule: +1% performance for at most +1% power consumption. | ||
− | |||
− | |||
=== Architecture === | === Architecture === | ||
Line 214: | Line 203: | ||
* 2 FP ALUs (1 adder, 1 for others) | * 2 FP ALUs (1 adder, 1 for others) | ||
* No Integer multiplier & divider (shared with FP ALU instead) | * No Integer multiplier & divider (shared with FP ALU instead) | ||
− | |||
− | |||
− | |||
=== Memory Hierarchy === | === Memory Hierarchy === | ||
Line 269: | Line 255: | ||
*** Large Pages | *** Large Pages | ||
**** 8 entries, 4-way set associative | **** 8 entries, 4-way set associative | ||
+ | |||
+ | === Block Diagram === | ||
+ | [[File:bonnell block diagram.svg]] | ||
=== Overview === | === Overview === | ||
− | Bonnell's architecture shares very little in common with other Intel designs. To achieve the strict ultra-low power objects, Bonnell features a very slimmed | + | Bonnell's architecture shares very little in common with other Intel designs. To achieve the strict ultra-low power objects, Bonnell features a very slimmed own design discarding many high-performance techniques used by Intel's high-performance architectures such as aggressive [[speculative execution]], [[out-of-order]] execution, and µop transformation. |
− | Part of the design requirement was that Bonnell retain full [[x86]] compatibility, up to the latest extension - at | + | Part of the design requirement was that Bonnell retain full [[x86]] compatibility, up to the latest extension - at the 10th of the power consumption of the {{\\|Pentium M}}. This meant any software is now 100% compatible but it forced engineers to deal with all the baggage the architecture brought along. The decision to offer full compatibility brought its own set of benefits such as access to the largest software code base in the world, including the ability to run any other [[x86]] operating system unmodified. At the same time it forced the design team to resort to other means of reducing power. |
− | |||
− | |||
+ | Up to Bonnell, all of Intel's existing architectures put very low priority on power efficiency (note that this has significantly changed since the introduction of {{\\|Sandy Bridge}}). High-performance, high-throughput, complex designs are simply inadequate for the kind of power goals required out of Bonnell, even if they were trimmed down. It was decided that Bonnel would be designed from the scratch with power goals in mind. For those reasons Bonnell resembles the {{\\|P5}} microarchitecture. | ||
=== Pipeline === | === Pipeline === | ||
Much like the original {{\\|P5}} microarchitecture, Bonnell consists of an [[in-order]] [[dual-issue]] pipeline. The pipeline is shown below. Note the pipeline is duplicated for dual-issue execution. | Much like the original {{\\|P5}} microarchitecture, Bonnell consists of an [[in-order]] [[dual-issue]] pipeline. The pipeline is shown below. Note the pipeline is duplicated for dual-issue execution. | ||
Line 284: | Line 272: | ||
− | Unlike {{\\|P5}}, which only had 5 stages, Bonnell has 16 to 19 pipeline | + | Unlike {{\\|P5}}, which only had 5 stages, Bonnell has 16 to 19 stages pipeline. The longer pipeline allows a more evenly spreading of heat across the chip with more units. This also allows a higher clock rate. |
==== Front End ==== | ==== Front End ==== | ||
− | Bonnell's front end is very simple when compared to Intel's high-performance architectures. [[Out-of-order execution]] (OoOE) that is found ubiquitously in all HPC architectures was rejected. Bonnell's power and area constraints simply couldn't allow for the complex logic needed to support that capability. The [[Instruction Fetch]] consists of 3 stages | + | Bonnell's front end is very simple when compared to Intel's high-performance architectures. [[Out-of-order execution]] (OoOE) that is found ubiquitously in all HPC architectures was rejected. Bonnell's power and area constraints simply couldn't allow for the complex logic needed to support that capability. The [[Instruction Fetch]] consists of 3 stages capable going through up to 16 bytes per cycle. Like fetch, the [[Instruction Decode]] is also 3 stages capable of decording instructions with up to 3 prefixes each cycle (considerably longer for more complex instructions). |
Bonnell is a departure from all modern x86 architectures with respect to decoding (including those developed by [[AMD]] and [[VIA]] and every Intel architecture since {{\\|P6}}). Whereas modern architectures transform complex [[x86]] instructions into a more easily digestible µop form, Bonnell does almost no such transformations. The pipeline is tailored to execute regular x86 instructions as single atomic operations consisting of a single destination register and up to three source-registers (typical load-operate-store format). Most instructions actually correspond very closely to the original x86 instructions. This design choice results in lower complexity but at the cost of performance reduction. Bonnell has two identical decoders capable of decoding complex x86 instructions. Being variable length instruction architecture introduces an additional layer of complexity. To assist the decoders, Bonnell implements predecoders that determine instruction boundaries and mark them using a single-bit marker. Two cycles are allocated for predecoding as well as L1 storage. Boundary marks are also stored in the L1 eliminating the need to preform needlessly redundant predecoding. Repeated operations are retrieved pre-marked eliminating two cycles. Bonnel has a 36 KiB L1 instruction cache consisting of 32 KiB instruction cache and 4 KiB instruction boundary mark cache. All instructions (coming from both cache or predecode) must undergo full decode. It's worthwhile noting that Intel states Bonnell is a 16-stage pipeline because for the most part, after a cache hit you'll have 16 stages. This is also true in some cases where the processor can simultaneously decode the next instruction. However, in the cases where you get a miss, it will cost 3 additional stages to catch up and locate the boundary for that instruction for a total of 19 stages. | Bonnell is a departure from all modern x86 architectures with respect to decoding (including those developed by [[AMD]] and [[VIA]] and every Intel architecture since {{\\|P6}}). Whereas modern architectures transform complex [[x86]] instructions into a more easily digestible µop form, Bonnell does almost no such transformations. The pipeline is tailored to execute regular x86 instructions as single atomic operations consisting of a single destination register and up to three source-registers (typical load-operate-store format). Most instructions actually correspond very closely to the original x86 instructions. This design choice results in lower complexity but at the cost of performance reduction. Bonnell has two identical decoders capable of decoding complex x86 instructions. Being variable length instruction architecture introduces an additional layer of complexity. To assist the decoders, Bonnell implements predecoders that determine instruction boundaries and mark them using a single-bit marker. Two cycles are allocated for predecoding as well as L1 storage. Boundary marks are also stored in the L1 eliminating the need to preform needlessly redundant predecoding. Repeated operations are retrieved pre-marked eliminating two cycles. Bonnel has a 36 KiB L1 instruction cache consisting of 32 KiB instruction cache and 4 KiB instruction boundary mark cache. All instructions (coming from both cache or predecode) must undergo full decode. It's worthwhile noting that Intel states Bonnell is a 16-stage pipeline because for the most part, after a cache hit you'll have 16 stages. This is also true in some cases where the processor can simultaneously decode the next instruction. However, in the cases where you get a miss, it will cost 3 additional stages to catch up and locate the boundary for that instruction for a total of 19 stages. | ||
Line 375: | Line 363: | ||
=== Modularity === | === Modularity === | ||
Bonnell is a highly modular architecture with almost all features disableable via built-in fuses allowing for many [[binning]] variation. Both virtualization support (VT-x/d) and {{intel|Hyper-Threading}} may be disabled to cut on power. Bonnell implements both AGTL+ and CMOS transceiver logic for the [[front-side bus]] signaling with either one capable of being fused off. CMOS signaling allows for lower power but cannot reach the high bug speeds that AGTL+ can. This may or maybe not be a restriction that system designers might face. | Bonnell is a highly modular architecture with almost all features disableable via built-in fuses allowing for many [[binning]] variation. Both virtualization support (VT-x/d) and {{intel|Hyper-Threading}} may be disabled to cut on power. Bonnell implements both AGTL+ and CMOS transceiver logic for the [[front-side bus]] signaling with either one capable of being fused off. CMOS signaling allows for lower power but cannot reach the high bug speeds that AGTL+ can. This may or maybe not be a restriction that system designers might face. | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
== Die == | == Die == | ||
Line 507: | Line 447: | ||
== Cores == | == Cores == | ||
− | + | === First Generation=== | |
− | + | First generation of Bonnell-based microprocessors introduced 2 cores: '''{{intel|Silverthorne|l=core}}''' for ultra-mobile PCs and mobile Internet devices (MIDs) and '''{{intel|Diamondville}}''' for ultra cheap notebooks and desktops. | |
− | + | ==== Silverthorne ==== | |
− | + | {{main|intel/cores/silverthorne|l1=Silverthorne}} | |
− | + | '''Silverthorne''' was the codename for a series of Mobile Internet Devices (MIDs) introduced in 2008. These processors had 1 core and 2 threads with a FSB operating at 400 MHz-533 MHz. | |
− | === First | + | ==== Diamondville ==== |
− | First generation of Bonnell-based microprocessors introduced 2 cores: '''{{intel|Silverthorne|l=core}}''' for ultra-mobile PCs and mobile Internet devices (MIDs) and '''{{intel|Diamondville}}''' for ultra cheap notebooks and desktops. | + | {{main|intel/diamondville|l1=Diamondville}} |
− | + | '''Diamondville''' was the codename for the series of ultra cheap notebooks and desktops introduced in 2008. Diamondville is very much a soldered-on-motherboard derivative of {{intel|Silverthorne|l=core}} with faster FSB (operating at 533 MHz - 667 MHz). The dual-core version is an MCM (Multi Chip Module) Silverthorne variant. | |
− | |||
− | |||
− | |||
=== Second Generation === | === Second Generation === | ||
First generation of Bonnell-based microprocessors while being low power had to work with the older [[90 nm process]] {{intel|945GSE}} chipset and {{intel|82801GBM}} I/O controller with a TDP of almost 9.5 watts - almost 4 times that of the processor itself. Second generation Bonnell-based microprocessors aimed to address this issue by integrating a memory controller and GPU on-chip. This drastically reduced power consumption and cost. | First generation of Bonnell-based microprocessors while being low power had to work with the older [[90 nm process]] {{intel|945GSE}} chipset and {{intel|82801GBM}} I/O controller with a TDP of almost 9.5 watts - almost 4 times that of the processor itself. Second generation Bonnell-based microprocessors aimed to address this issue by integrating a memory controller and GPU on-chip. This drastically reduced power consumption and cost. | ||
− | + | ==== Lincroft ==== | |
− | + | {{main|intel/lincroft|l1=Lincroft}} | |
− | + | '''Lincroft''' is the codename for Bonnell-based Silverthorne's successor. Lincroft integrates on-die the graphics and memory controller. | |
==== Pineview ==== | ==== Pineview ==== | ||
{{main|intel/pineview|l1=Pineview}} | {{main|intel/pineview|l1=Pineview}} | ||
Line 548: | Line 485: | ||
Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips | Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips | ||
--> | --> | ||
− | + | <table class="wikitable sortable"> | |
− | <table class=" | + | <tr><th colspan="11" style="background:#D6D6FF;">Bonnell Chips</th></tr> |
− | <tr | + | <tr><th colspan="8">CPU</th><th colspan="3">IGP</th></tr> |
− | <tr | + | <tr><th>Model</th><th>µarch</th><th>Platform</th><th>Core</th><th>Launched</th><th>SDP</th><th>Freq</th><th>Max Mem</th><th>Name</th><th>Freq</th><th>Max Freq</th></tr> |
− | + | {{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Bonnell]] | |
− | {{#ask: [[Category:microprocessor models by intel | ||
|?full page name | |?full page name | ||
|?model number | |?model number | ||
− | |? | + | |?microarchitecture |
+ | |?platform | ||
|?core name | |?core name | ||
|?first launched | |?first launched | ||
− | |? | + | |?sdp |
− | + | |?base frequency | |
− | |?base frequency | + | |?max memory |
− | |||
− | |||
− | |||
− | |||
− | |? | ||
|?integrated gpu | |?integrated gpu | ||
|?integrated gpu base frequency | |?integrated gpu base frequency | ||
− | |? | + | |?integrated gpu max frequency |
− | |||
− | |||
− | |||
|format=template | |format=template | ||
− | |template=proc table | + | |template=proc table 2 |
− | |userparam= | + | |userparam=12 |
|mainlabel=- | |mainlabel=- | ||
}} | }} | ||
− | |||
</table> | </table> | ||
− | |||
== Documents == | == Documents == | ||
* [[:File:Menlow Platform.pdf|Menlow Platform]] presentation | * [[:File:Menlow Platform.pdf|Menlow Platform]] presentation | ||
− | |||
== Artwork == | == Artwork == | ||
Line 608: | Line 534: | ||
* Wang, Perry H., et al. "Intel® atom™ processor core made FPGA-synthesizable." Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays. ACM, 2009. | * Wang, Perry H., et al. "Intel® atom™ processor core made FPGA-synthesizable." Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays. ACM, 2009. | ||
* Corporation, Intel. "Intel 64 and IA-32 architectures optimization reference manual." (2009). | * Corporation, Intel. "Intel 64 and IA-32 architectures optimization reference manual." (2009). | ||
− | |||
− | |||
− | |||
− | |||
− |
Facts about "Bonnell - Microarchitectures - Intel"
codename | Bonnell + |
core count | 1 + and 2 + |
designer | Intel + |
first launched | March 2, 2008 + |
full page name | intel/microarchitectures/bonnell + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Bonnell + |
phase-out | 2011 + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 16 + |
process | 45 nm (0.045 μm, 4.5e-5 mm) + |