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{{intel title|Bonnell|arch}} | {{intel title|Bonnell|arch}} | ||
{{microarchitecture | {{microarchitecture | ||
− | |atype=CPU | + | | atype = CPU |
− | |name=Bonnell | + | | name = Bonnell |
− | |designer=Intel | + | | designer = Intel |
− | |manufacturer=Intel | + | | manufacturer = Intel |
− | |introduction= | + | | introduction = 2008 |
− | |phase-out=2011 | + | | phase-out = 2011 |
− | |process=45 nm | + | | process = 45 nm |
− | |cores=1 | + | | cores = 1 |
− | |cores 2=2 | + | | cores 2 = 2 |
− | |type=Superscalar | + | |
− | | | + | | pipeline = Yes |
− | |speculative= | + | | type = Superscalar |
− | |renaming=No | + | | OoOE = No |
− | |stages min=16 | + | | speculative = No |
− | |stages max=19 | + | | renaming = No |
− | | | + | | isa = IA-32 |
− | |extension=MOVBE | + | | isa 2 = x86-64 |
− | |extension 2=MMX | + | | stages min = 16 |
− | |extension 3=SSE | + | | stages max = 19 |
− | |extension 4=SSE2 | + | | issues = 2 |
− | |extension 5=SSE3 | + | |
− | |extension 6=SSSE3 | + | | inst = Yes |
− | |l1i=32 KiB | + | | feature = |
− | |l1i per=Core | + | | extension = MOVBE |
− | |l1i desc=8-way set associative | + | | extension 2 = MMX |
− | |l1d=24 KiB | + | | extension 3 = SSE |
− | |l1d per=Core | + | | extension 4 = SSE2 |
− | |l1d desc=6-way set associative | + | | extension 5 = SSE3 |
− | |l2=512 KiB | + | | extension 6 = SSSE3 |
− | |l2 per=Core | + | |
− | |l2 desc=8-way set associative | + | | cache = Yes |
− | |core name=Silverthorne | + | | l1i = 32 KiB |
− | |core name 2=Diamondville | + | | l1i per = Core |
− | |core name 3=Lincroft | + | | l1i desc = 8-way set associative |
− | |core name 4=Pineview | + | | l1d = 24 KiB |
− | |core name 5=Tunnel Creek | + | | l1d per = Core |
− | |core name 6=Stellarton | + | | l1d desc = 6-way set associative |
− | |core name 7=Sodaville | + | | l2 = 512 KiB |
− | |core name 8=Groveland | + | | l2 per = Core |
− | |successor=Saltwell | + | | l2 desc = 8-way set associative |
− | |successor link=intel/microarchitectures/saltwell | + | |
− | + | | core names = Yes | |
− | + | | core name = Silverthorne | |
− | + | | core name 2 = Diamondville | |
− | + | | core name 3 = Lincroft | |
− | + | | core name 4 = Pineview | |
− | + | | core name 5 = Tunnel Creek | |
− | + | | core name 6 = Stellarton | |
+ | | core name 7 = Sodaville | ||
+ | | core name 8 = Groveland | ||
+ | |||
+ | | succession = Yes | ||
+ | | predecessor = | ||
+ | | successor = Saltwell | ||
+ | | successor link = intel/microarchitectures/saltwell | ||
}} | }} | ||
− | '''Bonnell''' was a [[microarchitecture]] for [[Intel]]'s [[45 nm]] ultra-low | + | '''Bonnell''' was a [[microarchitecture]] for [[Intel]]'s [[45 nm]] ultra-low power [[microprocessor]]s first introduced in 2008 for their then-new {{intel|Atom}} family. Bonnell, which was named after the highest point in [[wikipedia:Austin, Texas|Austin]] - [[wikipedia:Mount Bonnell|Mount Bonnell]], was Intel's first x86-compatible [[microarchitecture]] designed to target the ultra-low power market. |
− | Bonnell (project Silverthorne then) was designed by a then-new low-power design team Intel created at their Texas Development Center in Austin in 2004 along with a new chipset ( | + | Bonnell (project Silverthorne then) was designed by a then-new low-power design team Intel created at their Texas Development Center in Austin in 2004 along with a new chipset (Poulsbo) design team. The design team was led by Elinora Yoeli. While Yoeli previously worked at her native country, Bonnell was a US design and was unconnected to any of Intel's projects worked on by the Israel Design Center in Haifa. Previously Yoeli led the Israeli team in the development of {{\\|Pentium M}}. |
== Codenames == | == Codenames == | ||
− | |||
{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
− | ! Platform !! | + | ! Chipset !! Platform !! PHC !! Core !! Target |
|- | |- | ||
− | | {{intel| | + | | {{intel|Poulsbo}} || {{intel|Menlow}} || || {{intel|Silverthorne}} || MIDs |
|- | |- | ||
− | | {{intel| | + | | {{intel|Poulsbo}} || {{intel|Menlow}} || || {{intel|Diamondville}} || Nettops |
|- | |- | ||
− | | {{intel|Moorestown | + | | || {{intel|Moorestown}} || {{intel|Langwell}} || {{intel|Lincroft}} || MIDs |
|- | |- | ||
− | | {{intel|Pine Trail}} || {{intel|Tiger Point}} || {{intel|Pineview | + | | || {{intel|Pine Trail}} || {{intel|Tiger Point}} || {{intel|Pineview}} || Nettops |
|- | |- | ||
− | | {{intel|Queens Bay}} || {{intel|Topcliff}} || {{intel|Tunnel Creek | + | | || {{intel|Queens Bay}} || {{intel|Topcliff}} || {{intel|Tunnel Creek}} || Embedded |
|- | |- | ||
− | | {{intel|Queens Bay}} || {{intel|Topcliff}} || {{intel|Stellarton | + | | || {{intel|Queens Bay}} || {{intel|Topcliff}} || {{intel|Stellarton}} || Embedded + [[Altera]] FPGA |
|- | |- | ||
− | | || || {{intel|Sodaville | + | | || || || {{intel|Sodaville}} || CE |
|- | |- | ||
− | | | | + | | || || || {{intel|Groveland}} || CE |
− | |||
− | | || || {{intel| | ||
|} | |} | ||
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=== Generation successor === | === Generation successor === | ||
{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
− | ! First Generation !! !! Second | + | ! First Generation !! !! Second Generation |
|- | |- | ||
− | | {{intel|Silverthorne | + | | {{intel|Silverthorne}} || → || {{intel|Lincroft}} |
|- | |- | ||
− | | {{intel|Diamondville | + | | {{intel|Diamondville}} || → || {{intel|Pineview}} |
|- | |- | ||
− | | || || {{intel|Tunnel Creek | + | | || || {{intel|Tunnel Creek}} |
|- | |- | ||
− | | || || {{intel|Stellarton | + | | || || {{intel|Stellarton}} |
|- | |- | ||
− | | || || {{intel|Sodaville | + | | || || {{intel|Sodaville}} |
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|- | |- | ||
− | | | + | | || || {{intel|Groveland}} |
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|} | |} | ||
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== Release Dates == | == Release Dates == | ||
− | + | Bonnell was first announced on April 2nd [[2008]] during the Intel Developers Forum in Shanghai. | |
== Process Technology == | == Process Technology == | ||
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| SRAM bit cell (HD) || 0.346 µm² | | SRAM bit cell (HD) || 0.346 µm² | ||
|- | |- | ||
− | | SRAM bit cell (LP) || 0. | + | | SRAM bit cell (LP) || 0.382 µm² |
|} | |} | ||
{{clear}} | {{clear}} | ||
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== Compiler support == | == Compiler support == | ||
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== Architecture == | == Architecture == | ||
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Bonnell features a brand new architecture not based on any previous Intel design. The architecture was specifically designed for ultra-mobile PCs (UMPCs), mobile internet devices (MID), and other embedded devices. Bonnell's primary goals were: | Bonnell features a brand new architecture not based on any previous Intel design. The architecture was specifically designed for ultra-mobile PCs (UMPCs), mobile internet devices (MID), and other embedded devices. Bonnell's primary goals were: | ||
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Performance/Power new rule: +1% performance for at most +1% power consumption. | Performance/Power new rule: +1% performance for at most +1% power consumption. | ||
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=== Architecture === | === Architecture === | ||
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* [[45 nm process]], 9 metal layers, [[CMOS]] | * [[45 nm process]], 9 metal layers, [[CMOS]] | ||
* 500 mW to 2 W TDP | * 500 mW to 2 W TDP | ||
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* 533 MT/s dual mode ([[gunning transceiver logic|GTL]] & [[CMOS]]) [[front side bus|FSB]] | * 533 MT/s dual mode ([[gunning transceiver logic|GTL]] & [[CMOS]]) [[front side bus|FSB]] | ||
* In-order | * In-order | ||
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* 2 FP ALUs (1 adder, 1 for others) | * 2 FP ALUs (1 adder, 1 for others) | ||
* No Integer multiplier & divider (shared with FP ALU instead) | * No Integer multiplier & divider (shared with FP ALU instead) | ||
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=== Memory Hierarchy === | === Memory Hierarchy === | ||
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** C6 cache | ** C6 cache | ||
*** 10.5 KiB array to hold the architectural state during deep power down state | *** 10.5 KiB array to hold the architectural state during deep power down state | ||
− | |||
** L1 Instruction Cache | ** L1 Instruction Cache | ||
*** 36 [[KiB]] | *** 36 [[KiB]] | ||
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*** 1 read and 1 write port | *** 1 read and 1 write port | ||
*** 8 transistors (instead of 6) to reduce voltage | *** 8 transistors (instead of 6) to reduce voltage | ||
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** L1 Data Cache | ** L1 Data Cache | ||
*** 24 KiB | *** 24 KiB | ||
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*** 1 read and 1 write port | *** 1 read and 1 write port | ||
*** 8 transistors (instead of 6) to reduce voltage | *** 8 transistors (instead of 6) to reduce voltage | ||
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*** Per core | *** Per core | ||
** L2 Cache: | ** L2 Cache: | ||
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*** 64-bit cache line | *** 64-bit cache line | ||
*** Per core | *** Per core | ||
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** L3 Cache: | ** L3 Cache: | ||
*** No level 3 cache | *** No level 3 cache | ||
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=== Overview === | === Overview === | ||
− | Bonnell's architecture shares very little in common with other Intel designs. To achieve the strict ultra-low power objects, Bonnell features a very slimmed | + | Bonnell's architecture shares very little in common with other Intel designs. To achieve the strict ultra-low power objects, Bonnell features a very slimmed own design discarding many high-performance techniques used by Intel's high-performance architectures such as aggressive [[speculative execution]], [[out-of-order]] execution, and µop transformation. |
− | Part of the design requirement was that Bonnell retain full [[x86]] compatibility, up to the latest extension - at | + | Part of the design requirement was that Bonnell retain full [[x86]] compatibility, up to the latest extension - at the 10th of the power consumption of the {{\\|Pentium M}}. This meant any software is now 100% compatible but it forced engineers to deal with all the baggage the architecture brought along. The decision to offer full compatibility brought its own set of benefits such as access to the largest software code base in the world, including the ability to run any other [[x86]] operating system unmodified. At the same time it forced the design team to resort to other means of reducing power. |
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+ | Up to Bonnell, all of Intel's existing architectures put very low priority on power efficiency (note that this has significantly changed since the introduction of {{\\|Sandy Bridge}}). High-performance, high-throughput, complex designs are simply inadequate for the kind of power goals required out of Bonnell, even if they were trimmed down. It was decided that Bonnel would be designed from the scratch with power goals in mind. For those reasons Bonnell resembles the {{\\|P5}} microarchitecture. | ||
=== Pipeline === | === Pipeline === | ||
Much like the original {{\\|P5}} microarchitecture, Bonnell consists of an [[in-order]] [[dual-issue]] pipeline. The pipeline is shown below. Note the pipeline is duplicated for dual-issue execution. | Much like the original {{\\|P5}} microarchitecture, Bonnell consists of an [[in-order]] [[dual-issue]] pipeline. The pipeline is shown below. Note the pipeline is duplicated for dual-issue execution. | ||
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− | Unlike {{\\|P5}}, which only had 5 stages, Bonnell has 16 to 19 pipeline | + | Unlike {{\\|P5}}, which only had 5 stages, Bonnell has 16 to 19 stages pipeline. The longer pipeline allows a more evenly spreading of heat across the chip with more units. This also allows a higher clock rate. |
==== Front End ==== | ==== Front End ==== | ||
− | Bonnell's front end is very simple when compared to Intel's high-performance architectures. [[Out-of-order execution]] (OoOE) that is found ubiquitously in all HPC architectures was rejected. Bonnell's power and area constraints simply couldn't allow for the complex logic needed to support that capability. The [[Instruction Fetch]] consists of 3 stages | + | Bonnell's front end is very simple when compared to Intel's high-performance architectures. [[Out-of-order execution]] (OoOE) that is found ubiquitously in all HPC architectures was rejected. Bonnell's power and area constraints simply couldn't allow for the complex logic needed to support that capability. The [[Instruction Fetch]] consists of 3 stages capable going through up to 8 bytes per cycle (with a lower amount if SMT is enabled). Like fetch, the [[Instruction Decode]] is also 3 stages capable of decording instructions with up to 3 prefixes each cycle (considerably longer for more complex instructions). |
− | Bonnell is a departure from all modern x86 architectures with respect to decoding (including those developed by [[AMD]] and [[VIA]] and every Intel architecture since {{\\|P6}}). Whereas modern architectures transform complex [[x86]] instructions into a more easily digestible µop form, Bonnell does almost no such transformations | + | Bonnell is a departure from all modern x86 architectures with respect to decoding (including those developed by [[AMD]] and [[VIA]] and every Intel architecture since {{\\|P6}}). Whereas modern architectures transform complex [[x86]] instructions into a more easily digestible µop form, Bonnell does almost no such transformations. Most instructions actually correspond very closely to the original x86 instructions. This design choice results in lower complexity but at the cost of performance reduction. Bonnell has two identical decoders capable of decoding complex x86 instructions. Being variable length instruction architecture introduces additional complexity. To assist the decoders, Bonnell implements predecoders that determine instruction boundaries and mark them using a single-bit marker. Two cycles are allocated for predecoding as well as L1 storage. Boundary marks are also stored in the L1 eliminating the need to preform needlessly redundant predecoding. Repeated operations are retrieved pre-marked eliminating two cycles. Bonnel has a 36 KiB L1 instruction cache consisting of 32 KiB instruction cache and 4 KiB instruction boundary mark cache. All instructions (coming from both cache or predecode) must undergo full decode. It's worthwhile noting that Intel states Bonnell is a 16-stage pipeline because for the most part, after a cache hit you'll have 16 stages. This is also true in some cases where the processor can simultaneously decode the next instruction. However, in the cases where you get a miss, it will cost 3 additional stages to catch up and locate the boundary for that instruction for a total of 19 stages. |
− | Some x86 instructions are simply too complex to handle directly. Those selected few get diverted into the | + | Some x86 instructions are simply too complex to handle directly. Those selected few get diverted into the microcode sequencer for decoding producing much more sane RISCish instructions at the cost of 2 additional cycles. Intel estimates that only 5% of common software require instructions to be split up. The inability to execute things [[out-of-order]] eliminates lots of optimization opportunities at this stage. One thing Bonnell can do is lockstep instructions that can be execute simultaneously such as in the case of instructions that performance a memory access along an arithmetic operation. In those instances Bonnell will issue the instruction as if it were two separate instructions executing simultaneously. |
Because Bonnell has support for {{intel|Hyper-Threading}}, Intel's brand name for their own [[simultaneous multithreading]] technology, a number of modifications had to be done. The [[prefetch buffer]] and the [[instruction queue]] have been duplicated for each thread. | Because Bonnell has support for {{intel|Hyper-Threading}}, Intel's brand name for their own [[simultaneous multithreading]] technology, a number of modifications had to be done. The [[prefetch buffer]] and the [[instruction queue]] have been duplicated for each thread. | ||
===== Branch predictor ===== | ===== Branch predictor ===== | ||
− | No aggressive speculative execution is done in Bonnell, however it does implements a light-weight | + | No aggressive speculative execution is done in Bonnell, however it does implements a light-weight [[branch predictor]] consisting of a [[two-level adaptive predictor]] with a 12-bit global history table. The pattern history table has 4096 entries and is [[competitively shared]] between threads. The branch buffer target has 128 entries (4-way by 32 sets). While [[unconditional jumps]] are not recorded in the table, [[always-taken]] and [[never-taken]] jumps do. |
The branch-misprediction penalty is 11 to 13 cycles. Some of the rare or complex x86 instructions will detour into a microcode sequencer for decoding, necessitating two additional clock cycles. Additionally there is a roughly 7 cycle penalty for correctly predicted branches but no target can be predicted because of a missing [[branch target buffer]] (BTB) entry. Bonnell return stack buffer is 8-entry deep. | The branch-misprediction penalty is 11 to 13 cycles. Some of the rare or complex x86 instructions will detour into a microcode sequencer for decoding, necessitating two additional clock cycles. Additionally there is a roughly 7 cycle penalty for correctly predicted branches but no target can be predicted because of a missing [[branch target buffer]] (BTB) entry. Bonnell return stack buffer is 8-entry deep. | ||
==== Back End ==== | ==== Back End ==== | ||
− | + | Bonnell [[in-order]] back-end resembles a traditional early 90s design featuring a dual [[ALU]], a dual [[FPU]] and a dual [[AGU]]. Similarly to the front-end, in order to accommodate [[simultaneous multithreading]], the Bonnell design team chose to duplicate both the [[floating-point]] and [[integer]] [[register file]]s. The duplication of the register files allows Bonnell to perform context switching on each stage by maintaining duplicate states for each thread. The decision to duplicate this logic directly results in more transistors and larger area of the silicon. Overall implementing SMT still required less power and less die area than the other heavyweight alternatives (i.e., [[out-of-order]] and larger [[superscaler]]). | |
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=== Multithreading === | === Multithreading === | ||
Bonnell supports [[Intel]]'s {{intel|Hyper-Threading}}, their marketing term for their own implementation of simultaneous multithreading. The notion of implementing [[simultaneous multithreading]] on such a low-power architecture might seem unusual at first. In fact, it's one of only a handful of ultra-low power architectures to support such feature. Intel justified this design choice by demonstrating that performance enjoys an uplift of anywhere from 30% to 50% while worsening power consumption by up to 20% (with an average of 30% performance increase for 15% more power). The toll on the die area was a mere 8%. | Bonnell supports [[Intel]]'s {{intel|Hyper-Threading}}, their marketing term for their own implementation of simultaneous multithreading. The notion of implementing [[simultaneous multithreading]] on such a low-power architecture might seem unusual at first. In fact, it's one of only a handful of ultra-low power architectures to support such feature. Intel justified this design choice by demonstrating that performance enjoys an uplift of anywhere from 30% to 50% while worsening power consumption by up to 20% (with an average of 30% performance increase for 15% more power). The toll on the die area was a mere 8%. | ||
In the front-end, the [[prefetch buffer]] and the [[instruction queue]] have been duplicated for each thread, everything else is competitively shared between the threads. In the back-end, only the [[integer]] and [[floating]] [[register file]]s are duplicated, everything else is competitively shared as well. Note that both threads compete over the L1 instruction and data caches as well as the L2 and the TLBs with the exception of a 16-entry micro-TLB that's duplicated for each thread. | In the front-end, the [[prefetch buffer]] and the [[instruction queue]] have been duplicated for each thread, everything else is competitively shared between the threads. In the back-end, only the [[integer]] and [[floating]] [[register file]]s are duplicated, everything else is competitively shared as well. Note that both threads compete over the L1 instruction and data caches as well as the L2 and the TLBs with the exception of a 16-entry micro-TLB that's duplicated for each thread. | ||
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== Die == | == Die == | ||
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* [[45 nm process]] | * [[45 nm process]] | ||
* 9 metal layers | * 9 metal layers | ||
− | * 47, | + | * 47,000,000 transistors |
* 3.1 mm x 7.8 mm | * 3.1 mm x 7.8 mm | ||
− | * 24. | + | * 24.2 mm² die size |
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[[File:Silverthorne die shot.jpg|1100px]] | [[File:Silverthorne die shot.jpg|1100px]] | ||
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[[File:Silverthorne die shot (marked).png|1100px]] | [[File:Silverthorne die shot (marked).png|1100px]] | ||
− | + | * '''BIC''' - Bus Interface Cluster | |
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− | * '''BIC | ||
* '''MEC''' - Memory Cluster Execution & L1d$ | * '''MEC''' - Memory Cluster Execution & L1d$ | ||
* '''FPC''' - FP/SIMD execution Cluster | * '''FPC''' - FP/SIMD execution Cluster | ||
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* '''FEC''' - Front-End Cluster & L1i$ | * '''FEC''' - Front-End Cluster & L1i$ | ||
* '''FSB''' - Front Side Bus | * '''FSB''' - Front Side Bus | ||
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== Cores == | == Cores == | ||
− | + | === First Generation=== | |
− | + | First generation of Bonnell-based microprocessors introduced 2 cores: '''{{intel|Silverthorne}}''' for ultra-mobile PCs and mobile Internet devices (MIDs) and '''{{intel|Diamondville}}''' for ultra cheap notebooks and desktops. | |
− | + | ==== Silverthorne ==== | |
− | + | {{main|intel/silverthorne|l1=Silverthorne}} | |
− | + | '''Silverthorne''' was the codename for a series of Mobile Internet Devices (MIDs) introduced in 2008. These processors had 1 core and 2 threads with a FSB operating at 400 MHz-533 MHz. | |
− | === First | + | ==== Diamondville ==== |
− | First generation of Bonnell-based microprocessors introduced 2 cores: '''{{intel|Silverthorne | + | {{main|intel/diamondville|l1=Diamondville}} |
− | + | '''Diamondville''' was the codename for the series of ultra cheap notebooks and desktops introduced in 2008. Diamondville is very much a soldered-on-motherboard derivative of {{intel|Silverthorne}} with faster FSB (operating at 533 MHz - 667 MHz). The dual-core version is an MCM (Multi Chip Module) Silverthorne variant. | |
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=== Second Generation === | === Second Generation === | ||
First generation of Bonnell-based microprocessors while being low power had to work with the older [[90 nm process]] {{intel|945GSE}} chipset and {{intel|82801GBM}} I/O controller with a TDP of almost 9.5 watts - almost 4 times that of the processor itself. Second generation Bonnell-based microprocessors aimed to address this issue by integrating a memory controller and GPU on-chip. This drastically reduced power consumption and cost. | First generation of Bonnell-based microprocessors while being low power had to work with the older [[90 nm process]] {{intel|945GSE}} chipset and {{intel|82801GBM}} I/O controller with a TDP of almost 9.5 watts - almost 4 times that of the processor itself. Second generation Bonnell-based microprocessors aimed to address this issue by integrating a memory controller and GPU on-chip. This drastically reduced power consumption and cost. | ||
− | + | ==== Lincroft ==== | |
− | + | {{main|intel/lincroft|l1=Lincroft}} | |
− | + | '''Lincroft''' is the codename for Bonnell-based Silverthorne's successor. Lincroft integrates on-die the graphics and memory controller. | |
==== Pineview ==== | ==== Pineview ==== | ||
{{main|intel/pineview|l1=Pineview}} | {{main|intel/pineview|l1=Pineview}} | ||
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Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips | Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips | ||
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− | + | <table class="wikitable sortable"> | |
− | <table class=" | + | <tr><th colspan="11" style="background:#D6D6FF;">Bonnell Chips</th></tr> |
− | <tr | + | <tr><th colspan="8">CPU</th><th colspan="3">IGP</th></tr> |
− | <tr | + | <tr><th>Model</th><th>µarch</th><th>Platform</th><th>Core</th><th>Launched</th><th>SDP</th><th>Freq</th><th>Max Mem</th><th>Name</th><th>Freq</th><th>Max Freq</th></tr> |
− | + | {{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Bonnell]] | |
− | {{#ask: [[Category:microprocessor models by intel | ||
|?full page name | |?full page name | ||
|?model number | |?model number | ||
− | |? | + | |?microarchitecture |
+ | |?platform | ||
|?core name | |?core name | ||
|?first launched | |?first launched | ||
− | |? | + | |?sdp |
− | + | |?base frequency | |
− | |?base frequency | + | |?max memory |
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− | |? | ||
|?integrated gpu | |?integrated gpu | ||
|?integrated gpu base frequency | |?integrated gpu base frequency | ||
− | |? | + | |?integrated gpu max frequency |
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|format=template | |format=template | ||
− | |template=proc table | + | |template=proc table 2 |
− | |userparam= | + | |userparam=12 |
|mainlabel=- | |mainlabel=- | ||
}} | }} | ||
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</table> | </table> | ||
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Facts about "Bonnell - Microarchitectures - Intel"
codename | Bonnell + |
core count | 1 + and 2 + |
designer | Intel + |
first launched | March 2, 2008 + |
full page name | intel/microarchitectures/bonnell + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Bonnell + |
phase-out | 2011 + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 16 + |
process | 45 nm (0.045 μm, 4.5e-5 mm) + |