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{{intel title|Kaby Lake U|core}} | {{intel title|Kaby Lake U|core}} | ||
{{core | {{core | ||
− | |name=Kaby Lake | + | | name = Kaby Lake U |
− | + | | developer = Intel | |
− | + | | manufacturer = Intel | |
− | + | | first announced = August 30, 2016 | |
− | + | | first launched = August 30, 2016 | |
− | + | | isa = x86-64 | |
− | + | | microarch = Kaby Lake | |
− | |developer=Intel | + | | word = 64 bit |
− | |manufacturer=Intel | + | | proc = 14 nm |
− | |first announced=August 30, 2016 | + | | tech = CMOS |
− | |first launched=August 30, 2016 | + | | clock min = |
− | |isa=x86-64 | + | | clock max = |
− | |microarch=Kaby Lake | + | | package = FCBGA-1356 |
− | |word=64 bit | + | | socket = BGA-1356 |
− | |proc=14 nm | + | |
− | |tech=CMOS | + | | succession = Yes |
− | |clock min= | + | | predecessor = Skylake U |
− | |clock max= | + | | predecessor link = intel/cores/skylake u |
− | |package | + | | successor = Cannonlake U |
− | |predecessor=Skylake U | + | | successor link = intel/cores/cannonlake u |
− | |predecessor link=intel/cores/skylake u | ||
− | |successor= | ||
− | |||
− | |||
− | |successor | ||
}} | }} | ||
− | '''Kaby Lake U''' ('''KBL-U''') is the name of the core for [[Intel]]'s line of low-power mobile processors based on the {{intel|Kaby Lake|l=arch}} microarchitecture serving as a successor to {{intel|Skylake U|l=core}}. These chips are primarily targeted towards light notebooks and laptops, portable | + | '''Kaby Lake U''' ('''KBL-U''') is the name of the core for [[Intel]]'s line of low-power mobile processors based on the {{intel|Kaby Lake|l=arch}} microarchitecture serving as a successor to {{intel|Skylake U|l=core}} core. These chips are primarily targeted towards light notebooks and laptops, portable All-in-Ones (AiOs), Minis, and conference rooms. Kaby Lake U processors are fabricated on Intel's enhanced [[14 nm lithography process|14nm+ process]] and provide {{intel|kaby_lake#Key_changes_from_Skylake|slight enhancements over|l=arch}} comparable Skylake models. |
== Overview == | == Overview == | ||
− | Kaby Lake U based processors are a single-chip solution - the chipset is packaged in the same physical casing as the CPU in a [[multi-chip package]] (MCP). Note that some models (the Iris [[IGP]]s) are actually a 3 dice chip configuration since they incorporate an on-package cache (OPC) in addition to the hub and CPU. Communication between the separate dies are done via a lightweight On-Package Interconnect (OPI) interface, allowing for 4 GT/s transfer rate. All | + | Kaby Lake U based processors are a single-chip solution - the chipset is packaged in the same physical casing as the CPU in a [[multi-chip package]] (MCP). Note that some models (the Iris [[IGP]]s) are actually a 3 dice chip configuration since they incorporate an on-package cache (OPC) in addition to the hub and CPU. Communication between the separate dies are done via a lightweight On-Package Interconnect (OPI) interface, allowing for 4 GT/s transfer rate. All Iris models include 64 MiB of 4th level cache (See {{intel|Crystal Well}}). |
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=== Common Features === | === Common Features === | ||
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All Kaby Lake U processors have the following: | All Kaby Lake U processors have the following: | ||
* Dual-channel Memory | * Dual-channel Memory | ||
− | ** Up to LPDDR3-1866, DDR3L-1600, | + | ** Up to LPDDR3-1866, DDR3L-1600, DDR4-2133 |
** Up to 16-64 GiB | ** Up to 16-64 GiB | ||
* 12x PCIe | * 12x PCIe | ||
− | * [[dual-core]] with 4 threads ({{intel|Celeron}} models only have 2 threads as they have {{intel|Hyper-Threading}} disabled | + | * [[dual-core]] with 4 threads ({{intel|Celeron}} models only have 2 threads as they have {{intel|Hyper-Threading}} disabled}} |
− | * Everything up to | + | * Everything up to AVX (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX) (not all S models support {{x86|AVX2}}) |
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* Graphics | * Graphics | ||
− | ** {{intel|HD Graphics 610}} (Gen 9.5 LP GT1), {{intel|HD Graphics 620}} ( | + | ** {{intel|HD Graphics 610}} (Gen 9.5 LP GT1), {{intel|HD Graphics 620}} (Gen 9.5 LP GT2), or {{intel|Iris Plus Graphics 640}}/{{intel|Iris Plus Graphics 650|650}} (Gen 9.5 LP GT3e) |
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** Base frequency of 350 MHz | ** Base frequency of 350 MHz | ||
** Burst frequency of 1-1.15 GHz | ** Burst frequency of 1-1.15 GHz | ||
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== Kaby Lake U Processors == | == Kaby Lake U Processors == | ||
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|?integrated gpu base frequency | |?integrated gpu base frequency | ||
|?integrated gpu max frequency | |?integrated gpu max frequency | ||
− | |?has intel turbo boost technology | + | |?has intel turbo boost technology 2.0 |
|?has simultaneous multithreading | |?has simultaneous multithreading | ||
|?has advanced vector extensions 2 | |?has advanced vector extensions 2 | ||
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== See also == | == See also == | ||
− | {{intel | + | * {{intel|Kaby Lake|l=arch}} |
− | * {{intel| | + | ** {{intel|Kaby Lake Y|l=core}} |
− | ** {{intel|Skylake U|l=core}} | + | ** {{intel|Kaby Lake H|l=core}} |
+ | ** {{intel|Kaby Lake S|l=core}} | ||
+ | * {{intel|Skylake U|l=core}} | ||
+ | * {{intel|Goldmont|l=arch}} |
Facts about "Kaby Lake U - Cores - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Kaby Lake U - Cores - Intel#package + |
designer | Intel + |
first announced | August 30, 2016 + |
first launched | August 30, 2016 + |
instance of | core + |
isa | x86-64 + |
main image | + and + |
main image caption | 3-die config Iris Plus KBL-U (with OPC) + and 2-die config KBL-U + |
manufacturer | Intel + |
microarchitecture | Kaby Lake + |
name | Kaby Lake U + |
package | FCBGA-1356 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |