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{{core | {{core | ||
|name=Cascade Lake SP | |name=Cascade Lake SP | ||
− | |image= | + | |image=skylake sp (basic).png |
+ | |image 2=skylake-sp (hfi).png | ||
+ | |caption 2=Skylake SP, with HFI | ||
|developer=Intel | |developer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
− | |first announced= | + | |first announced=May 16, 2017 |
− | |first launched= | + | |first launched=December 2018 |
|isa=x86-64 | |isa=x86-64 | ||
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|microarch=Cascade Lake | |microarch=Cascade Lake | ||
|platform=Purley | |platform=Purley | ||
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|successor=Ice Lake SP | |successor=Ice Lake SP | ||
|successor link=intel/cores/ice lake sp | |successor link=intel/cores/ice lake sp | ||
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}} | }} | ||
− | '''Cascade Lake SP''' ('''{{intel|Cascade Lake|l=arch}} Scalable Performance''') is code name for Intel's series of server [[multiprocessors]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture as part of the {{intel|Purley|l=platform}} platform serving as the successor to {{intel|Skylake SP|l=core}}. These chips support up to 8-way multiprocessing, up to [[28 cores]], incorporate a new {{x86|AVX512-VNNI|AVX512}} [[x86]] {{x86|extension}} for neural network / deep learning workloads | + | '''Cascade Lake SP''' ('''{{intel|Cascade Lake|l=arch}} Scalable Performance''') is code name for Intel's series of server [[multiprocessors]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture as part of the {{intel|Purley|l=platform}} platform serving as the successor to {{intel|Skylake SP|l=core}}. These chips support up to 8-way multiprocessing, up to [[28 cores]], and incorporate a new {{x86|AVX512-VNNI|AVX512}} [[x86]] {{x86|extension}} for neural network / deep learning workloads. Cascade Lake SP-based chips are manufactured on an enhanced [[14 nm process|14nm++ process]] and utilize the {{intel|Lewisburg|l=chipset}} chipset. Cascade Lake SP-based models are branded as the {{intel|Xeon Bronze}}, {{intel|Xeon Silver}}, {{intel|Xeon Gold}}, and {{intel|Xeon Platinum}} [[processor families]]. |
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− | Cascade Lake SP-based models are branded as the | ||
== Overview == | == Overview == | ||
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=== Common Features === | === Common Features === | ||
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{{clear}} | {{clear}} | ||
− | === | + | == Cascade Lake SP Processors == |
− | + | {{future information}} | |
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<!-- NOTE: | <!-- NOTE: | ||
This table is generated automatically from the data in the actual articles. | This table is generated automatically from the data in the actual articles. | ||
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<table class="comptable sortable tc5 tc6 tc14"> | <table class="comptable sortable tc5 tc6 tc14"> | ||
{{comp table header|main|12:List of Cascade Lake SP-based Processors}} | {{comp table header|main|12:List of Cascade Lake SP-based Processors}} | ||
− | {{comp table header|main|8:Main Processor| | + | {{comp table header|main|8:Main Processor|2:Cache|2:Memory}} |
− | {{comp table header|cols|Family|Price|Launched|Cores|Threads|Frequency|Max Turbo|%TDP|L3$|Mem Type|Max Mem | + | {{comp table header|cols|Family|Price|Launched|Cores|Threads|Frequency|Max Turbo|%TDP|L2$|L3$|Mem Type|Max Mem}} |
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{{comp table header|lsep|25:[[Multiprocessors]] (2-way)}} | {{comp table header|lsep|25:[[Multiprocessors]] (2-way)}} | ||
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Cascade Lake SP]] [[max cpu count::2]] | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Cascade Lake SP]] [[max cpu count::2]] | ||
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|?turbo frequency (1 core)#GHz | |?turbo frequency (1 core)#GHz | ||
|?tdp | |?tdp | ||
+ | |?l2$ size | ||
|?l3$ size | |?l3$ size | ||
|?supported memory type | |?supported memory type | ||
− | |?max memory# | + | |?max memory#GiB |
|format=template | |format=template | ||
|template=proc table 3 | |template=proc table 3 | ||
− | |userparam= | + | |userparam=14 |
|mainlabel=- | |mainlabel=- | ||
|limit=75 | |limit=75 | ||
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|sort=model number | |sort=model number | ||
}} | }} | ||
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|?turbo frequency (1 core)#GHz | |?turbo frequency (1 core)#GHz | ||
|?tdp | |?tdp | ||
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|?l3$ size | |?l3$ size | ||
|?supported memory type | |?supported memory type | ||
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|format=template | |format=template | ||
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|sort=model number | |sort=model number | ||
}} | }} | ||
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|?turbo frequency (1 core)#GHz | |?turbo frequency (1 core)#GHz | ||
|?tdp | |?tdp | ||
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|?l3$ size | |?l3$ size | ||
|?supported memory type | |?supported memory type | ||
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|template=proc table 3 | |template=proc table 3 | ||
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|sort=model number | |sort=model number | ||
}} | }} | ||
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</table> | </table> | ||
{{comp table end}} | {{comp table end}} | ||
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== See also == | == See also == | ||
{{intel cascade lake core see also}} | {{intel cascade lake core see also}} |
Facts about "Cascade Lake SP - Cores - Intel"
chipset | Lewisburg + |
designer | Intel + |
first announced | April 2, 2019 + |
first launched | April 2, 2019 + |
instance of | core + |
isa | x86-64 + |
isa family | x86 + |
main image | + |
manufacturer | Intel + |
microarchitecture | Cascade Lake + |
name | Cascade Lake SP + |
package | FCLGA-3647 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | Socket P + and LGA-3647 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |