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== Architecture == | == Architecture == | ||
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=== Key changes from {{\\|TaiShan v100}} === | === Key changes from {{\\|TaiShan v100}} === | ||
* [[TSMC]] [[7 nm|7 nm HPC process]] (from [[16 nm]]) | * [[TSMC]] [[7 nm|7 nm HPC process]] (from [[16 nm]]) | ||
* 2x [[core count]] (64, up from 32) | * 2x [[core count]] (64, up from 32) | ||
** Custom cores (from {{armh|Cortex-A72|l=arch}}) | ** Custom cores (from {{armh|Cortex-A72|l=arch}}) | ||
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{{expand list}} | {{expand list}} | ||
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** L1I Cache | ** L1I Cache | ||
*** 64 KiB/core, private | *** 64 KiB/core, private | ||
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** L1D Cache | ** L1D Cache | ||
*** 64 KiB/core, private | *** 64 KiB/core, private | ||
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** L2 Cache | ** L2 Cache | ||
*** 512 KiB/core, private | *** 512 KiB/core, private | ||
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== Overview == | == Overview == | ||
[[File:taishan v110 overview.svg|right|500px|thumb|Overview]] | [[File:taishan v110 overview.svg|right|500px|thumb|Overview]] | ||
− | Though HiSilicon has a history of designing Arm processors. The TaiShan v110 core is HiSilicons' first custom homegrown high-performance [[ARM]] core and SoC design. The chip, which incorporates multiple compute dies and an I/O is a multi-chip package, is fabricated on [[TSMC]]'s [[7 nm | + | Though HiSilicon has a history of designing Arm processors. The TaiShan v110 core is HiSilicons' first custom homegrown high-performance [[ARM]] core and SoC design. The chip, which incorporates multiple compute dies and an I/O is a multi-chip package, is fabricated on [[TSMC]]'s [[7 nm process]] and integrates up to 64 cores and up to 64 MiB of [[last level cache]]. |
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Marketed as the Kunpeng 920, this SoC supports up to 4-way multiprocessing support through HiSilicon's Hydra interface. In order to keep the cores fed, eight [[DDR4]] [[memory channels]] are incorporated per socket. Additionally, designed to facilitate an easy [[accelerator]] platform, there are 40 PCIe Gen 4 lanes provided per socket with [[CCIX]] support, enabling cache coherency. | Marketed as the Kunpeng 920, this SoC supports up to 4-way multiprocessing support through HiSilicon's Hydra interface. In order to keep the cores fed, eight [[DDR4]] [[memory channels]] are incorporated per socket. Additionally, designed to facilitate an easy [[accelerator]] platform, there are 40 PCIe Gen 4 lanes provided per socket with [[CCIX]] support, enabling cache coherency. | ||
== Core == | == Core == | ||
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== MCP physical design == | == MCP physical design == | ||
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== Scalability == | == Scalability == | ||
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Each chip incorporates three Hydra interface ports. The Hydra interface facilitates the cache coherency between the dies on the chip. Every link supports 240 Gb/s (30 GB/s) of peak bandwidth for a total aggregated bandwidth of 720 Gb/s (90 GB/s) in a 2-way [[symmetric multiprocessing]] configuration. | Each chip incorporates three Hydra interface ports. The Hydra interface facilitates the cache coherency between the dies on the chip. Every link supports 240 Gb/s (30 GB/s) of peak bandwidth for a total aggregated bandwidth of 720 Gb/s (90 GB/s) in a 2-way [[symmetric multiprocessing]] configuration. | ||
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:[[File:Kunpeng 920 4smp.svg|600px]] | :[[File:Kunpeng 920 4smp.svg|600px]] | ||
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== Die == | == Die == | ||
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** 3-4 dies | ** 3-4 dies | ||
− | == All TaiShan | + | == All TaiShan Chips == |
− | {{ | + | {{empty section}} |
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== Bibliography == | == Bibliography == | ||
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* Huawei Connect 2018. October 2018 | * Huawei Connect 2018. October 2018 | ||
* HiSilicon Event. January 7, 2019 | * HiSilicon Event. January 7, 2019 | ||
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Facts about "TaiShan v110 - Microarchitectures - HiSilicon"
codename | TaiShan v110 + |
core count | 32 +, 48 + and 64 + |
designer | HiSilicon + |
first launched | 2019 + |
full page name | hisilicon/microarchitectures/taishan v110 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.2-A + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | TaiShan v110 + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + |