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== Architecture == | == Architecture == | ||
− | + | * [[TSMC]] [[7 nm|7 nm HPC process]] | |
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− | * [[TSMC]] [[7 nm|7 nm HPC process]] | ||
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{{expand list}} | {{expand list}} | ||
=== Block Diagram === | === Block Diagram === | ||
==== Entire Chip ==== | ==== Entire Chip ==== | ||
− | :[[File:taishan | + | :[[File:taishan soc block diagram.svg|900px]] |
=== Memory Hierarchy === | === Memory Hierarchy === | ||
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** L1I Cache | ** L1I Cache | ||
*** 64 KiB/core, private | *** 64 KiB/core, private | ||
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** L1D Cache | ** L1D Cache | ||
*** 64 KiB/core, private | *** 64 KiB/core, private | ||
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** L2 Cache | ** L2 Cache | ||
*** 512 KiB/core, private | *** 512 KiB/core, private | ||
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== Overview == | == Overview == | ||
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== Core == | == Core == | ||
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== Scalability == | == Scalability == | ||
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Each chip incorporates three Hydra interface ports. The Hydra interface facilitates the cache coherency between the dies on the chip. Every link supports 240 Gb/s (30 GB/s) of peak bandwidth for a total aggregated bandwidth of 720 Gb/s (90 GB/s) in a 2-way [[symmetric multiprocessing]] configuration. | Each chip incorporates three Hydra interface ports. The Hydra interface facilitates the cache coherency between the dies on the chip. Every link supports 240 Gb/s (30 GB/s) of peak bandwidth for a total aggregated bandwidth of 720 Gb/s (90 GB/s) in a 2-way [[symmetric multiprocessing]] configuration. | ||
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:[[File:Kunpeng 920 4smp.svg|600px]] | :[[File:Kunpeng 920 4smp.svg|600px]] | ||
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== Die == | == Die == | ||
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** 3-4 dies | ** 3-4 dies | ||
− | == All TaiShan | + | == All TaiShan Chips == |
− | {{ | + | {{empty section}} |
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== Bibliography == | == Bibliography == | ||
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* Huawei Connect 2018. October 2018 | * Huawei Connect 2018. October 2018 | ||
* HiSilicon Event. January 7, 2019 | * HiSilicon Event. January 7, 2019 | ||
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Facts about "TaiShan v110 - Microarchitectures - HiSilicon"
codename | TaiShan v110 + |
core count | 32 +, 48 + and 64 + |
designer | HiSilicon + |
first launched | 2019 + |
full page name | hisilicon/microarchitectures/taishan v110 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.2-A + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | TaiShan v110 + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + |