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− | {{dec title|Process Technology | + | {{dec title|Process Technology}} |
− | This article details details '''[[DEC]]'s [[ | + | This article details details '''[[DEC]]'s [[Semiconductor Process Technology]]''' history for research and posterity. |
The table below shows the history of DEC's process scaling. Values were taken from various DEC documents including historical presentations and journals, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between DEC's own documents and therefore discrepancies may exist. | The table below shows the history of DEC's process scaling. Values were taken from various DEC documents including historical presentations and journals, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between DEC's own documents and therefore discrepancies may exist. | ||
== Timeline == | == Timeline == | ||
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<div style="overflow-x: auto;" class="scrollable"> | <div style="overflow-x: auto;" class="scrollable"> | ||
<table class="wikitable" style="text-align: center;"> | <table class="wikitable" style="text-align: center;"> | ||
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}} | }} | ||
{{dec proc tech |year=1991 |name=CMOS-4 |mlayers=3 |node=0.75 µm | {{dec proc tech |year=1991 |name=CMOS-4 |mlayers=3 |node=0.75 µm | ||
− | |archs=Alpha 21064 | + | |archs=NVAX, Alpha 21064 |
|a1=T<sub>ox</sub> |d1=10.5 nm |a12=Masks |d12=21 | |a1=T<sub>ox</sub> |d1=10.5 nm |a12=Masks |d12=21 | ||
|a2=V<sub>dd</sub> |d2=3.3 V |a22=SRAM |d22= 100 µm² | |a2=V<sub>dd</sub> |d2=3.3 V |a22=SRAM |d22= 100 µm² | ||
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}} | }} | ||
{{dec proc tech |year=1994 |name=CMOS-5 |mlayers=4 |node=0.50 µm | {{dec proc tech |year=1994 |name=CMOS-5 |mlayers=4 |node=0.50 µm | ||
− | |archs= | + | |archs=NVAX++ |
− | |a1=T<sub>ox</sub> |d1= | + | |a1=T<sub>ox</sub> |d1= |
− | |a2 | + | |a2=L<sub>g</sub> |d2=0.50 µm |
− | |||
}} | }} | ||
{{dec proc tech |year=1996 |name=CMOS-6 |mlayers=4 |node=0.35 µm | {{dec proc tech |year=1996 |name=CMOS-6 |mlayers=4 |node=0.35 µm | ||
− | |archs= | + | |archs= |
|a1=T<sub>ox</sub> |d1=6 nm | |a1=T<sub>ox</sub> |d1=6 nm | ||
|a2=L<sub>g</sub> |d2=0.35 µm |a22=L<sub>eff</sub> |d22=0.25 µm | |a2=L<sub>g</sub> |d2=0.35 µm |a22=L<sub>eff</sub> |d22=0.25 µm | ||
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|a1=T<sub>ox</sub> |d1= | |a1=T<sub>ox</sub> |d1= | ||
}} | }} | ||
− | <tr><td>1997</td><td colspan="8" | + | <tr><td>1997</td><td colspan="8">Fab-6 in Hudson, Mass was sold to [[Intel]] which consequently upgraded it for $800M to Intel's propiatery [[0.18 µm]] (see {{intel|Process|Intel's Process}}).</td></tr> |
− | <tr><td>2013</td><td colspan="8 | + | <tr><td>2013</td><td colspan="8">In late 2013 Intel announced that it will be closing the Hudson Fab due to no longer meeting their requirements such as aging technology.</td></tr> |
</table> | </table> | ||
</div> | </div> | ||
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|} | |} | ||
− | == | + | <!-- |
− | + | |a12=Gate Dielectric |d12=SiO<sub>2</sub> | |
+ | |a2=V<sub>dd</sub> |d2=5 V |a22=SRAM |d22= 1120 µm² | ||
+ | |a3=L<sub>g</sub> |d3=3.0 µm | ||
+ | |a4=CPP |d4=7 µm |a42=MMP |d42= | ||
+ | --> |