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== Etymology == | == Etymology == | ||
The microarchitecture name '''Alpha 21064''' is composed of both the [[ISA]] and the [[microarchitecture|implementation]]. In particular, the "Alpha" refers to [[DEC]]'s [[Alpha AXP]] instruction set architecture while the "21064" refers to a "21st century"-ready {{arch|64}} "generation 0" microarchitecture. | The microarchitecture name '''Alpha 21064''' is composed of both the [[ISA]] and the [[microarchitecture|implementation]]. In particular, the "Alpha" refers to [[DEC]]'s [[Alpha AXP]] instruction set architecture while the "21064" refers to a "21st century"-ready {{arch|64}} "generation 0" microarchitecture. | ||
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== Release Dates == | == Release Dates == | ||
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* [[0.75 µm process]] | * [[0.75 µm process]] | ||
− | * 150-200 MHz (6.6-5 | + | * 150-200 MHz (6.6-5 nm cycles) |
* FP Unit | * FP Unit | ||
** Support for [[IEEE 754]] | ** Support for [[IEEE 754]] | ||
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* [[0.75 µm process]] | * [[0.75 µm process]] | ||
* 3 metal layers | * 3 metal layers | ||
− | * 1, | + | * 1,680,000 transistors |
− | * 13. | + | * 13.9 mm x 16.8 mm |
− | * | + | * 233.52 mm² die size |
* PGA-431 | * PGA-431 | ||
** 291 signal pins | ** 291 signal pins |
Facts about "Alpha 21064 - Microarchitectures - DEC"
codename | Alpha 21064 + |
core count | 1 + |
designer | DEC + |
first launched | November 20, 1992 + |
full page name | dec/microarchitectures/alpha 21064 + |
instance of | microarchitecture + |
instruction set architecture | Alpha + |
manufacturer | DEC + |
microarchitecture type | CPU + |
name | Alpha 21064 + |
pipeline stages (max) | 12 + |
pipeline stages (min) | 7 + |
process | 750 nm (0.75 μm, 7.5e-4 mm) + and 675 nm (0.675 μm, 6.75e-4 mm) + |