Editing cmos

{{title|CMOS - Complementary Metal–Oxide–Semiconductor}}
{{semi devices}}

'''CMOS''' ('''complementary [[metal–oxide–semiconductor]]''') is a technique for constructing analog and digital logic circuits from two complementary [[mosfet|MOS]] [[transistor]]s - [[pmos transistor|pMOS]] and [[pMOS transistor|nMOS]].  CMOS is the dominant technology used for [[VLSI]] and [[ULSI]] circuit chips used for anywhere from [[SRAM]] to [[microcontroller]]s and [[microprocessor]]s.

CMOS, also known as '''complementary-symmetry metal–oxide–semiconductor''' ('''COS-MOS'''), is a type of [[MOSFET|metal–oxide–semiconductor field-effect transistor]] (MOSFET) [[semiconductor device fabrication|fabrication process]] that uses complementary and symmetrical pairs of [[p-type semiconductor|p-type]] and [[n-type semiconductor|n-type]] MOSFETs for logic functions.<ref>{{cite article |title=What is CMOS Memory? |url=http://wickedsago.blogspot.com/2011/04/what-is-cmos-memory.html |work=Wicked Sago |accessdate=3 March 2013 |url-status=live |archiveurl=https://web.archive.org/web/20140926064548/http://wickedsago.blogspot.com/2011/04/what-is-cmos-memory.html |archivedate=26 September 2014 }}</ref> CMOS technology is used for constructing [[integrated circuit]] (IC) chips, including [[microprocessor]]s, [[microcontroller]]s, [[memory chip]]s (including [[Nonvolatile BIOS memory|CMOS BIOS]]), and other [[digital logic]] circuits. CMOS technology is also used for [[analog circuit]]s such as [[image sensor]]s ([[CMOS sensor]]s), [[data conversion|data converters]], [[RF circuit]]s ([[RF CMOS]]), and highly integrated [[transceiver]]s for many types of communication.

[[Mohamed M. Atalla]] and [[Dawon Kahng]] invented the MOSFET at [[Bell Labs]] in 1959, and then demonstrated the [[PMOS logic|PMOS]] (p-type MOS) and [[NMOS logic|NMOS]] (n-type MOS) fabrication processes in 1960. These processes were later combined and adapted into the complementary MOS (CMOS) process by [[Chih-Tang Sah]] and [[Frank Wanlass]] at [[Fairchild Semiconductor]] in 1963. [[RCA]] commercialized the technology with the trademark "COS-MOS" in the late 1960s, forcing other manufacturers to find another name, leading to "CMOS" becoming the standard name for the technology by the early 1970s. CMOS eventually overtook NMOS as the dominant MOSFET fabrication process for [[very large-scale integration]] (VLSI) chips in the 1980s, while also replacing earlier [[transistor–transistor logic]] (TTL) technology. CMOS has since remained the standard fabrication process for MOSFET [[semiconductor device]]s in VLSI chips. As of 2011, 99% of IC chips, including most [[digital electronics|digital]], [[analog integrated circuit|analog]] and [[mixed-signal]] ICs, are fabricated using CMOS technology.<ref>{{cite book |last1=Voinigescu |first1=Sorin |title=High-Frequency Integrated Circuits |date=2013 |publisher=[[Cambridge University Press]] |isbn=9780521873024 |page=164 |url=https://books.google.com/books?id=71dHe1yb9jgC&pg=PA164}}</ref>

== Overview ==
{{main|/complementary topology|l1=CMOS Complementary Topology}}

CMOS primarily makes use of what would otherwise be two separate circuit technologies - [[pmos transistor|pMOS]] and [[nMOS transistor|nMOS]]. To better understand this, consider an [[nMOS transistor]]. Because it can pull no higher than V<sub>DD</sub> - V<sub>t</sub> we get a degraded 1 output. Likewise with pMOS, we can pull no lower than V<sub>t</sub> - a degraded 0 output. By combining both types, we can borrow the desired characteristics from both transistors such as a strong 0 and a strong 1.
[[File:cmos comp topo.gif|right]]
CMOS circuits are designed with that concept in mind - always consisting of two separate sub-circuits called a '''PUN''' ({{cmos|pull-up network}}) and a '''PDN''' ({{cmos|pull-down network}}). CMOS logic must therefore by in one of two defined stages: 
* PUN is open; PDN is conducting
* PUN is conducting; PDN is open
Conceptually they can be thought of as two switches, one controlling the connection between the output and V<sub>DD</sub> and one controlling the connection between the output and GND. Therefore it's important to note that if both switches are closed or both switches are open, the output will be ambiguous. The concept of a [[/complementary topology|complementary topology]] ensures this does not happen. It should be noted that as the voltage on the transistor's gate changes, for a very brief moment both switches will be closed thereby creating a momentary spike in power consumption. This does become a problem with high frequency CMOS.

=== Inverter Example ===
{{main|inverter}}
[[File:cmos inverter.svg|thumb|right|125px|CMOS [[NOT gate]]]]
The simplest gate that can be implemented is the [[NOT gate]] which simply inverts the input. We can implement an inverter using a single nMOS and pMOS transistors. The pMOS transistor is connected to V<sub>DD</sub> while the nMOS transistor is connected to GND. When ''A'' is 0, the nMOS transistor turns OFF and the pMOS transistor turns ON. This results in ''Q'' being pulled up to 1 since the pMOS transistor will conduct V<sub>DD</sub>. Conversely, when ''A'' is 1, the nMOS transistor turns ON and the pMOS transistor turns OFF, thereby pulling ''Q'' down to GND.

== Logic Families/Types ==
The use of static CMOS circuits with the standard {{cmos|pull-up network|PUN}} and {{cmos|pull-down network|PDN}} networks are used in the vast majority computational logic in integrated circuits. They are fast, low power, and have good noise margins. Perhaps the primary reason the majority of circuits are designed using static CMOS is simply due to the fact that its universally supported by CAD tools and as in [[standard cell libraries]]. Sometimes, however, specialized applications might have constraints that exceed what static CMOS can provide, for example power or area restrictions. For those occasions, various other CMOS logic families have been devised, each with their own advantages and disadvantages. Some of the common ones are listed below.

===Static CMOS===
{{main|cmos/static|l1=Static CMOS}}
Also called Full CMOS logic, static CMOS is the most commonly used logic style. Static logic provides high noise immunity, low static power consumption, and has relatively high test coverage. It does pose a number of weaknesses such as high fan-out load, and somewhat high noise generation.

=== Pseudo-NMOS Logic=== 
{{main|cmos/pseudo-nmos|l1=Pseudo-NMOS Logic}}
Pseudo-NMOS Logic circuit simply uses a pMOS transistor to satisfy CMOS's [[/complementary topology|complementary topology]]. This type of logic allow high speed and low transistor count. However because of this very design, the output will experience reduced voltage swings and is thus susceptible to noise. When used sparingly, this circuit can provide substantial performance benefits at a cost of a small increase in static-power consumption. Additionally, when not used, the [[pMOS transistor]] can be used turned off shutting down the circuit at no additional cost.

===Dynamic CMOS===
{{main|cmos/dynamic|l1=Dynamic CMOS}}
Dynamic CMOS uses a clocked pMOS {{cmos|pull-up network|PUN}}. This type of circuit has two phases: '''precharge''' and '''evaluation'''. When the clock is LOW, the output node is precharged to V<sub>DD</sub> (note that no current flows because the [[nMOS transistor]] is off). Once the clock goes back to HIGH the evaluation phase kicks in and the output will depend on the evaluation of the logic function implemented. Because inputs are hooked up to the nMOS transistors, the load capacitance is also smaller. This also makes it faster than static CMOS. Despite having almost half the number of transistors, this type of circuit still consumes more power than static CMOS due to the constant need to precharge and discharge of the output even if the input does not change. A side effect of this is that dynamic gates that are connected to the same [[clock signal]] cannot be directly cascaded since the monotonically falling output is not a suitable input to a second dynamic gate expecting monotonically rising signals.

====Domino Logic====
{{main|cmos/domino|l1=Domino Logic|cmos/multiple-output domino logic|l2=Multiple-Output Domino Logic (MODL)}}
Domino logic solves the monotonicity problem in dynamic gates by placing a static CMOS inverter between cascading dynamic gates. The use of the inverter converts the monotonically falling output node into a rising one which is suitable for the next gate. The name '''domino gate''' is given to this dynamic-static CMOS pair because of its resemblance the behavior of domino tiles - all the gates are precharged simultaneously whereas the evaluation phase occurs sequentially.

====Dual-rail Domino Logic====
{{main|cmos/dual-rail domino|l1=Dual-rail Domino Logic}}
{{empty section}}

==== NP Domino (Zipper) ====
{{main|cmos/np domino|l1=NP Domino}}
{{empty section}}

===Pass-Transistor Logic (PTL)===
{{main|cmos/pass-transistor|l1=Pass-Transistor Logic}}
In Pass-Transistor Logic (PTL), inputs drive both gate terminals and source/drain terminals. In specialized circumstances, PTL can be significantly improve the speed, power, and area of the logic. In general, PTL usually yields equivalent logic to static CMOS - especially those making heavy use of [[transmission gate]]s. PTL is not regenerative degrading the output as you chain them.

==== Complementary Pass-Transistor Logic (CPTL)====
{{main|cmos/complementary pass-transistor|l1=Complementary Pass-Transistor Logic}}
Complementary Pass-Transistor Logic (CPTL) is a more specialized version of Pass-Transistor Logic which makes use of both the inputs and their complements. Likewise both the output and its complement gets generated.

====  Lean Integration with Pass Transistors (LEAP) ====
{{main|cmos/lean integration with pass transistors|l1=Lean Integration with Pass Transistors}}
{{empty section}}

=== Cascade Voltage Switch Logic (CVSL) ===
{{main|cmos/cascade voltage switch logic|l1=Cascade Voltage Switch Logic (CVSL)}}
{{empty section}}

== History ==
{{Further|MOSFET|Transistor density}}
[[File:Atalla1963.png|thumb|[[Mohamed M. Atalla]] invented the [[PMOS]] and [[NMOS]] processes in 1960. The two processes were later combined into the CMOS process.]]

The [[MOSFET]] (metal-oxide-semiconductor field-effect transistor, or MOS transistor) was invented by [[Mohamed M. Atalla]] and [[Dawon Kahng]] at [[Bell Labs]] in 1959. There were originally two types of MOSFET [[Semiconductor device fabrication|fabrication processes]], [[PMOS logic|PMOS]] ([[p-type semiconductor|p-type]] MOS) and [[NMOS logic|NMOS]] ([[n-type semiconductor|n-type]] MOS).<ref name="computerhistory">{{cite article|url=https://www.computerhistory.org/siliconengine/metal-oxide-semiconductor-mos-transistor-demonstrated/|title=1960: Metal Oxide Semiconductor (MOS) Transistor Demonstrated|journal=The Silicon Engine: A Timeline of Semiconductors in Computers|publisher=[[Computer History Museum]] |accessdate=August 31, 2019}}</ref> Both types were developed by Atalla and Kahng when they originally invented the MOSFET, fabricating both PMOS and NMOS devices with [[20 µm process|20&nbsp;µm]] and then [[10 µm process|10&nbsp;µm]] gate lengths in 1960.<ref name="Lojek">{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=[[Springer Science & Business Media]] |isbn=9783540342588 |pages=321–3}}</ref><ref>{{cite book |last1=Voinigescu |first1=Sorin |title=High-Frequency Integrated Circuits |date=2013 |publisher=[[Cambridge University Press]]|isbn=978-0521873024 |page=164 |url=https://books.google.com/books?id=71dHe1yb9jgC&pg=PA164}}</ref> While the MOSFET was initially overlooked and ignored by Bell Labs in favour of [[bipolar transistors]],<ref name="Lojek"/> the MOSFET invention generated significant interest at [[Fairchild Semiconductor]].<ref name="computerhistory"/> Based on Atalla's work,<ref name="Sah">{{cite article |last=Sah |first=Chih-Tang |author-link=Chih-Tang Sah |title=Evolution of the MOS transistor-from conception to VLSI |journal=[[Proceedings of the IEEE]] |date=October 1988 |volume=76 |issue=10 |pages=1280–1326 (1290) |doi=10.1109/5.16328 |bibcode=1988IEEEP..76.1280S |url=http://www.dejazzer.com/ece723/resources/Evolution_of_the_MOS_transistor.pdf |issn=0018-9219 |quote=Those of us active in silicon material and device research during 1956{{ndash}}1960 considered this successful effort by the Bell Labs group led by Atalla to stabilize the silicon surface the most important and significant technology advance, which blazed the trail that led to silicon integrated circuit technology developments in the second phase and volume production in the third phase.}}</ref> [[Chih-Tang Sah]] introduced MOS technology to Fairchild with his MOS-controlled [[tetrode]] fabricated in late 1960.<ref name="computerhistory"/>

A new type of MOSFET logic combining both the PMOS and NMOS processes was developed, called complementary MOS (CMOS), by Chih-Tang Sah and [[Frank Wanlass]] at Fairchild. In February 1963, they published the invention in a [[Academic paper|research paper]].<ref name="computerhistory1963">{{cite article |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |accessdate=6 July 2019}}</ref><ref name="sah">{{cite article |last1=Sah |first1=Chih-Tang |author1-link=Chih-Tang Sah |last2=Wanlass |first2=Frank |author2-link=Frank Wanlass |title=Nanowatt logic using field-effect metal-oxide semiconductor triodes |journal=1963 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |date=1963 |volume=VI |pages=32–33 |doi=10.1109/ISSCC.1963.1157450}}</ref> Wanlass later filed [[s:United States patent 3356858|US patent 3,356,858]] for CMOS circuitry in June 1963, and it was granted in 1967. In both the research paper and the [[patent]], the fabrication of CMOS devices was outlined, on the basis of [[thermal oxidation]] of a silicon substrate to yield a layer of [[silicon dioxide]] located between the drain contact and the source contact.<ref>[http://www.freepatentsonline.com/3356858.pdf Low stand-by power complementary field effect circuitry]</ref><ref name="sah"/>

CMOS was commercialised by [[RCA]] in the late 1960s. RCA adopted CMOS for the design of [[integrated circuit]]s (ICs), developing CMOS circuits for an [[United States Air Force|Air Force]] computer in 1965 and then a 288-[[bit]] CMOS [[Static random-access memory|SRAM]] memory chip in 1968.<ref name="computerhistory1963"/> RCA also used CMOS for its [[4000-series integrated circuits]] in 1968, starting with a 20$nbsp;[[μm]] [[semiconductor manufacturing process]] before gradually scaling to a [[10&nbsp;μm process]] over the next several years.<ref name="Lojek330">{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=[[Springer Science & Business Media]] |isbn=9783540342588 |page=330 |url=https://books.google.com/books?id=2cu1Oh_COv8C&pg=PA330}}</ref>

CMOS technology was initially overlooked by the American [[semiconductor industry]] in favour of NMOS, which was more powerful at the time. However, CMOS was quickly adopted and further advanced by Japanese semiconductor manufacturers due to its low power consumption, leading to the rise of the Japanese semiconductor industry.<ref>{{cite book |last1=Gilder |first1=George |title=Microcosm: The Quantum Revolution In Economics And Technology |date=1990 |publisher=[[Simon and Schuster]] |isbn=9780671705923 |pages=[https://archive.org/details/microcosm00geor/page/144 144]–5 |url=https://archive.org/details/microcosm00geor|url-access=registration }}</ref> [[Toshiba]] developed C²MOS (Clocked CMOS), a circuit technology with lower [[power consumption]] and faster operating speed than ordinary CMOS, in 1969. Toshiba used its C²MOS technology to develop a [[large-scale integration]] (LSI) chip for [[Sharp Corporation|Sharp]]'s Elsi Mini [[LED]] [[pocket calculator]], developed in 1971 and released in 1972.<ref>{{cite article |title=1972 to 1973: CMOS LSI circuits for calculators (Sharp and Toshiba) |url=http://www.shmj.or.jp/english/pdf/ic/exhibi707E.pdf |website=Semiconductor History Museum of Japan |accessdate=5 July 2019 |archive-url=https://web.archive.org/web/20190706035338/http://www.shmj.or.jp/english/pdf/ic/exhibi707E.pdf |archive-date=2019-07-06 |url-status=dead }}</ref> [[Suwa Seikosha]] (now [[Seiko Epson]]) began developing a CMOS IC chip for a [[Seiko]] [[quartz watch]] in 1969, and began mass-production with the launch of the [[Seiko]] Analog Quartz 38SQW watch in 1971.<ref>{{cite article |title=Early 1970s: Evolution of CMOS LSI circuits for watches |url=http://www.shmj.or.jp/english/pdf/ic/exhibi757E.pdf |website=Semiconductor History Museum of Japan |accessdate=6 July 2019 |archive-url=https://web.archive.org/web/20190706144338/http://www.shmj.or.jp/english/pdf/ic/exhibi757E.pdf |archive-date=6 July 2019 |url-status=dead }}</ref> The first mass-produced CMOS consumer electronic product was the [[Hamilton Watch Company|Hamilton]] Pulsar "Wrist Computer" digital watch, released in 1970.<ref name="computerhistory-digital">{{cite article |title=Tortoise of Transistors Wins the Race - CHM Revolution |url=https://www.computerhistory.org/revolution/digital-logic/12/279 |website=[[Computer History Museum]] |accessdate=22 July 2019}}</ref> Due to low power consumption, CMOS logic has been widely used for [[calculators]] and [[watches]] since the 1970s.<ref name="shmj">{{cite article |title=1978: Double-well fast CMOS SRAM (Hitachi) |url=http://www.shmj.or.jp/english/pdf/ic/exhibi727E.pdf |website=Semiconductor History Museum of Japan |accessdate=5 July 2019 |archive-url=https://web.archive.org/web/20190705234921/http://www.shmj.or.jp/english/pdf/ic/exhibi727E.pdf |archive-date=5 July 2019 |url-status=dead }}</ref>

The [[microprocessor chronology|earliest microprocessors]] in the early 1970s were PMOS processors, which initially dominated the early [[microprocessor]] industry. By the late 1970s, NMOS microprocessors had overtaken PMOS processors.<ref name="Kuhn">{{cite book |last1=Kuhn |first1=Kelin |title=High Mobility Materials for CMOS Applications |date=2018 |publisher=[[Woodhead Publishing]] |isbn=9780081020623 |chapter=CMOS and Beyond CMOS: Scaling Challenges |page=1 |chapter-url=https://books.google.com/books?id=sOJgDwAAQBAJ&pg=PA1}}</ref> CMOS microprocessors were introduced in 1975, with the [[Intersil 6100]],<ref name="Kuhn"/> and RCA [[CDP 1801]].<ref>{{cite article |title=CDP 1800 μP Commercially available |journal=Microcomputer Digest |volume=2 |issue=4 |pages=1–3 |date=October 1975 |url=http://www.bitsavers.org/pdf/microcomputerAssociates/Microcomputer_Digest_v02n04_Oct75.pdf }}</ref> However, CMOS processors did not become dominant until the 1980s.<ref name="Kuhn"/>

CMOS was initially slower than [[NMOS logic]], thus NMOS was more widely used for computers in the 1970s.<ref name="shmj"/> The [[Intel]] 5101 (1$nbsp;[[kibibit|kb]] [[Static random-access memory|SRAM]]) CMOS memory chip (1974) had an [[access time]] of 800$nbsp;[[Nanosecond|ns]],<ref>{{cite article |title=Silicon Gate MOS 2102A |url=https://drive.google.com/file/d/0B9rh9tVI0J5mMmZlYWRlMDQtNDYzYS00OWJkLTg4YzYtZDYzMzc5Y2ZlYmVk/view |publisher=[[Intel]] |accessdate=27 June 2019}}</ref><ref name="Intel-Product-Timeline">{{cite article|url=http://download.intel.com/museum/research/arc_collect/timeline/TimelineDateSort7_05.pdf|title=A chronological list of Intel products. The products are sorted by date.|date=July 2005|work=Intel museum|publisher=Intel Corporation|archiveurl=https://web.archive.org/web/20070809053720/http://download.intel.com/museum/research/arc_collect/timeline/TimelineDateSort7_05.pdf|archivedate=August 9, 2007|accessdate=July 31, 2007}}</ref> whereas the fastest NMOS chip at the time, the Intel 2147 (4$nbsp;kb SRAM) [[HMOS]] memory chip (1976), had an access time of 55/70$nbsp;ns.<ref name="shmj"/><ref name="Intel-Product-Timeline"/> In 1978, a [[Hitachi]] research team led by Toshiaki Masuhara introduced the twin-well Hi-CMOS process, with its HM6147 (4$nbsp;kb SRAM) memory chip, manufactured with a [[3 μm process]].<ref name="shmj"/><ref>{{cite article |last1=Masuhara |first1=Toshiaki |last2=Minato |first2=Osamu |last3=Sasaki |first3=Toshio |last4=Sakai |first4=Yoshio |last5=Kubo |first5=Masaharu |last6=Yasui |first6=Tokumasa |title=A high-speed, low-power Hi-CMOS 4K static RAM |journal=1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |date=February 1978 |volume=XXI |pages=110–111 |doi=10.1109/ISSCC.1978.1155749|s2cid=30753823 }}</ref><ref>{{cite article |last1=Masuhara |first1=Toshiaki |last2=Minato |first2=Osamu |last3=Sakai |first3=Yoshi |last4=Sasaki |first4=Toshio |last5=Kubo |first5=Masaharu |last6=Yasui |first6=Tokumasa |title=Short Channel Hi-CMOS Device and Circuits |journal=ESSCIRC 78: 4th European Solid State Circuits Conference - Digest of Technical Papers |date=September 1978 |pages=131–132 |url=https://ieeexplore.ieee.org/document/5469023}}</ref> The Hitachi HM6147 chip was able to match the performance (55/70$nbsp;ns access) of the Intel 2147 HMOS chip, while the HM6147 also consumed significantly less power (15$nbsp;[[Milliamp|mA]]) than the 2147 (110$nbsp;mA). With comparable performance and much less power consumption, the twin-well CMOS process eventually overtook NMOS as the most common [[semiconductor manufacturing process]] for computers in the 1980s.<ref name="shmj"/>

In the 1980s, CMOS microprocessors overtook NMOS microprocessors.<ref name="Kuhn"/> [[NASA]]'s [[Galileo (spacecraft)|Galileo]] spacecraft, sent to orbit [[Jupiter]] in 1989, used the [[RCA 1802]] CMOS microprocessor due to low power consumption.<ref name="computerhistory-digital"/>

Intel introduced a [[1.5 μm process]] for CMOS [[semiconductor device fabrication]] in 1983.<ref name="Gealow">{{cite article |last1=Gealow |first1=Jeffrey Carl |title=Impact of Processing Technology on DRAM Sense Amplifier Design |url=https://core.ac.uk/download/pdf/4426308.pdf |publisher=[[Massachusetts Institute of Technology]] |website=[[COnnecting REpositories|CORE]] |date=10 August 1990 |pages=149–166 |accessdate=25 June 2019}}</ref>  In the mid-1980s, [[Bijan Davari]] of [[IBM]] developed high-performance, low-voltage, [[nanoelectronics|deep sub-micron]] CMOS technology, which enabled the development of faster computers as well as [[Mobile computer|portable computers]] and battery-powered [[handheld electronics]].<ref name="recipients">{{cite article |title=IEEE Andrew S. Grove Award Recipients |url=https://www.ieee.org/about/awards/bios/grove-recipients.html |website=IEEE Andrew S. Grove Award |publisher=[[Institute of Electrical and Electronics Engineers]] |accessdate=4 July 2019}}</ref> In 1988, Davari led an IBM team that demonstrated a high-performance [[250 nanometer]] CMOS process.<ref name="Davari1988">{{cite article|last1=Davari |display-authors=etal |first1=Bijan|title=A high-performance 0.25 micrometer CMOS technology|journal=International Electron Devices Meeting|date=1988|doi=10.1109/IEDM.1988.32749 |s2cid=114078857 }}</ref>

[[Fujitsu]] commercialized a 700$nbsp;[[Nanometre|nm]] CMOS process in 1987,<ref name="Gealow"/> and then Hitachi, [[Mitsubishi Electric]], [[NEC]] and Toshiba commercialized [[500 nanometer|500$nbsp;nm]] CMOS in 1989.<ref name="stol">{{cite article|url=http://maltiel-consulting.com/Semiconductor_technology_memory.html|title=Memory|website=STOL (Semiconductor Technology Online)|accessdate=25 June 2019}}</ref> In 1993, [[Sony]] commercialized a [[350 nanometer|350$nbsp;nm]] CMOS process, while Hitachi and NEC commercialized [[250 nanometer|250$nbsp;nm]] CMOS. Hitachi introduced a [[180 nanometer|160$nbsp;nm]] CMOS process in 1995, then Mitsubishi introduced 150$nbsp;nm CMOS in 1996, and then [[Samsung Electronics]] introduced 140$nbsp;nm in 1999.<ref name="stol"/>

In 2000, [[Gurtej Sandhu|Gurtej Singh Sandhu]] and Trung T. Doan at [[Micron Technology]] invented [[atomic layer deposition]] [[High-κ dielectric]] [[Thin film|films]], leading to the development of a cost-effective [[90&nbsp;nm]] CMOS process.<ref name="recipients"/><ref>{{cite article |last1=Sandhu |first1=Gurtej |last2=Doan |first2=Trung T. |title=Atomic layer doping apparatus and method |url=https://patents.google.com/patent/WO2002038841A3 |website=[[Google Patents]] |accessdate=5 July 2019 |date=22 August 2001}}</ref> Toshiba and Sony developed a [[65 nm]] CMOS process in 2002,<ref>{{cite article |title=Toshiba and Sony Make Major Advances in Semiconductor Process Technologies |url=https://www.toshiba.co.jp/about/press/2002_12/pr0301.htm |accessdate=26 June 2019 |work=[[Toshiba]] |date=3 December 2002}}</ref> and then [[TSMC]] initiated the development of [[45 nm]] CMOS logic in 2004.<ref>{{cite article |title=A Banner Year: TSMC Annual Report 2004 |url=https://www.tsmc.com/download/ir/annualReports/2004/2004e.pdf |publisher=[[TSMC]] |accessdate=5 July 2019}}</ref> The development of pitch [[double patterning]] by Gurtej Singh Sandhu at Micron Technology led to the development of [[32 nanometer|30$nbsp;nm]] class CMOS in the 2000s.<ref name="recipients"/>

CMOS is used in most modern LSI and [[VLSI]] devices.<ref name="shmj"/> As of 2010, [[CPUs]] with the best [[performance per watt]] each year have been CMOS [[Static logic (digital logic)|static logic]] since 1976. As of 2019, planar CMOS technology is still the most common form of semiconductor device fabrication, but is gradually being replaced by non-planar [[FinFET]] technology, which is capable of manufacturing [[semiconductor node]]s smaller than [[20 nanometer|20$nbsp;nm]].<ref>{{cite article |title=Global FinFET Technology Market 2024 Growth Analysis by Manufacturers, Regions, Type and Application, Forecast Analysis |url=https://financialplanning24.com/global-finfet-technology-market-2024-growth-analysis-by-manufacturers-regions-type-and-application-forecast-analysis/ |accessdate=6 July 2019 |work=Financial Planning |date=July 3, 2019}}</ref>

=== Timeline ===
{| class="wikitable sortable"
|+Complementary [[MOSFET]] ([[CMOS]]) demonstrations (single-[[metal gate|gate]])
!Date
! data-sort-type="number" |[[MOSFET#Structure and channel formation|Channel length]]
! data-sort-type="number" | [[Gate oxide|Oxide thickness]]<ref name="collins2">{{cite article|title=Angstrom|url=https://www.collinsdictionary.com/dictionary/english/angstrom|website=[[Collins English Dictionary]]|access-date=2019-03-02}}</ref>
!Researcher(s)
!Organization
! Ref
|-
| 1963-02
| ?
| ?
|[[Chih-Tang Sah]], [[Frank Wanlass]]
|[[Fairchild Semiconductor]]
|<ref name="computerhistory19633">{{cite article|title=1963: Complementary MOS Circuit Configuration is Invented|url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/|website=[[Computer History Museum]]|access-date=6 July 2019}}</ref><ref name="sah3">{{cite article|last1=Sah|first1=Chih-Tang|author1-link=Chih-Tang Sah|last2=Wanlass|first2=Frank|author2-link=Frank Wanlass|title=Nanowatt logic using field-effect metal–oxide semiconductor triodes|conference=1963 IEEE International Solid-State Circuits Conference. Digest of Technical Papers|date=February 1963|volume=VI|pages=32–33|doi=10.1109/ISSCC.1963.1157450}}</ref>
|-
|1968
|20,000 [[Nanometre|nm]]
|[[130 nanometer|{{#expr:1000/10}} nm]]
| ?
|[[RCA Laboratories]]
|<ref name="Lojek3303">{{cite book |last1=Lojek |first1=Bo |url=https://books.google.com/books?id=2cu1Oh_COv8C&pg=PA330 |title=History of Semiconductor Engineering |date=2007 |publisher=[[Springer Science & Business Media]] |isbn=9783540342588 |page=330}}</ref>
|-
|1970
|[[10 μm process|10,000 nm]]
|{{#expr:1000/10}} nm
| ?
|RCA Laboratories
|<ref name="Lojek3303" />
|-
| 1976-12
|[[3 μm process|2,000 nm]]
| ?
|A. Aitken, R.G. Poulsen, A.T.P. MacArthur, J.J. White
|[[Mitel|Mitel Semiconductor]]
|<ref>{{cite article|last1=Aitken|first1=A.|last2=Poulsen|first2=R. G.|last3=MacArthur|first3=A. T. P.|last4=White|first4=J. J.|title=1976 International Electron Devices Meeting|chapter=A fully plasma etched-ion implanted CMOS process|conference=1976 International Electron Devices Meeting|date=December 1976|pages=209–213|doi=10.1109/IEDM.1976.189021|s2cid=24526762}}</ref>
|-
| 1978-02
|[[3 μm process|3,000 nm]]
| ?
|Toshiaki Masuhara, Osamu Minato, Toshio Sasaki, Yoshio Sakai
|[[Hitachi|Hitachi Central Research Laboratory]] 
| <ref name="shmj3">{{cite article|title=1978: Double-well fast CMOS SRAM (Hitachi)|url=http://www.shmj.or.jp/english/pdf/ic/exhibi727E.pdf|website=Semiconductor History Museum of Japan|access-date=5 July 2019}}</ref><ref>{{cite article|last1=Masuhara|first1=Toshiaki|last2=Minato|first2=Osamu|last3=Sasaki|first3=Toshio|last4=Sakai|first4=Yoshio|last5=Kubo|first5=Masaharu|last6=Yasui|first6=Tokumasa|title=1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers|chapter=A high-speed, low-power Hi-CMOS 4K static RAM|conference=1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers|date=February 1978|volume=XXI|pages=110–111|doi=10.1109/ISSCC.1978.1155749|s2cid=30753823}}</ref><ref>{{cite article|last1=Masuhara|first1=Toshiaki|last2=Minato|first2=Osamu|last3=Sakai|first3=Yoshi|last4=Sasaki|first4=Toshio|last5=Kubo|first5=Masaharu|last6=Yasui|first6=Tokumasa|title=Short Channel Hi-CMOS Device and Circuits|journal=ESSCIRC 78: 4th European Solid State Circuits Conference – Digest of Technical Papers|date=September 1978|pages=131–132|url=https://ieeexplore.ieee.org/document/5469023}}</ref>
|-
| rowspan="2" | 1983-02
|[[1.5 μm process|1,200 nm]] 
|[[32 nanometer|{{#expr:250/10}} nm]]
|R.J.C. Chwang, M. Choi, D. Creek, S. Stern, P.H. Pelley 
|[[Intel]] 
|<ref name="Gealow3">{{cite article|last1=Gealow|first1=Jeffrey Carl|title=Impact of Processing Technology on DRAM Sense Amplifier Design|url=https://core.ac.uk/download/pdf/4426308.pdf|publisher=[[Massachusetts Institute of Technology]]|via=[[CORE (research service)|CORE]]|date=10 August 1990|pages=149–166|access-date=25 June 2019}}</ref><ref>{{cite book |last1=Chwang |first1=R. J. C. |title=1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |last2=Choi |first2=M. |last3=Creek |first3=D. |last4=Stern |first4=S. |last5=Pelley |first5=P. H. |last6=Schutz |first6=Joseph D. |last7=Bohr |first7=M. T. |last8=Warkentin |first8=P. A. |last9=Yu |first9=K. |date=February 1983 |volume=XXVI |pages=56–57 |chapter=A 70ns high density CMOS DRAM |doi=10.1109/ISSCC.1983.1156456 |s2cid=29882862}}</ref>
|-
|[[1 μm process|900 nm]]
|[[16 nanometer|{{#expr:150/10}} nm]]
|Tsuneo Mano, J. Yamada, Junichi Inoue, S. Nakajima
|[[Nippon Telegraph and Telephone]] (NTT) 
| <ref name="Gealow3" /><ref>{{cite book |last1=Mano |first1=Tsuneo |title=1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |last2=Yamada |first2=J. |last3=Inoue |first3=Junichi |last4=Nakajima |first4=S. |date=February 1983 |volume=XXVI |pages=234–235 |chapter=Submicron VLSI memory circuits |doi=10.1109/ISSCC.1983.1156549 |s2cid=42018248}}</ref>
|-
| 1983-12
|[[1 μm process|1,000 nm]]
|[[28 nanometer|{{#expr:225/10}} nm]]
|G.J. Hu, Yuan Taur, [[Robert H. Dennard]], Chung-Yu Ting 
|[[IBM T.J. Watson Research Center]]
|<ref>{{cite book |last1=Hu |first1=G. J. |title=1983 International Electron Devices Meeting |last2=Taur |first2=Yuan |last3=Dennard |first3=Robert H. |author3-link=Robert H. Dennard |last4=Terman |first4=L. M. |last5=Ting |first5=Chung-Yu |date=December 1983 |pages=739–741 |chapter=A self-aligned 1-μm CMOS technology for VLSI |doi=10.1109/IEDM.1983.190615 |s2cid=20070619}}</ref>
|-
| rowspan="2" | 1987-02
|[[800 nanometer|800 nm]]
|[[20 nanometer|17 nm]]
|T. Sumi, Tsuneo Taniguchi, Mikio Kishimoto, Hiroshige Hirano
|[[Panasonic|Matsushita]]
|<ref name="Gealow3" /><ref>{{cite book |last1=Sumi |first1=T. |title=1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |last2=Taniguchi |first2=Tsuneo |last3=Kishimoto |first3=Mikio |last4=Hirano |first4=Hiroshige |last5=Kuriyama |first5=H. |last6=Nishimoto |first6=T. |last7=Oishi |first7=H. |last8=Tetakawa |first8=S. |date=1987 |volume=XXX |pages=282–283 |chapter=A 60ns 4Mb DRAM in a 300mil DIP |doi=10.1109/ISSCC.1987.1157106 |s2cid=60783996}}</ref>
|-
|700&nbsp;nm
|[[12 nm]]
| Tsuneo Mano, J. Yamada, Junichi Inoue, S. Nakajima
|Nippon Telegraph and Telephone (NTT)
|<ref name="Gealow3" /><ref>{{cite book |last1=Mano |first1=Tsuneo |title=1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |last2=Yamada |first2=J. |last3=Inoue |first3=Junichi |last4=Nakajima |first4=S. |last5=Matsumura |first5=Toshiro |last6=Minegishi |first6=K. |last7=Miura |first7=K. |last8=Matsuda |first8=T. |last9=Hashimoto |first9=C. |date=1987 |volume=XXX |pages=22–23 |chapter=Circuit technologies for 16Mb DRAMs |doi=10.1109/ISSCC.1987.1157158 |last10=Namatsu |first10=H. |s2cid=60984466}}</ref>
|-
| 1987-09
|[[500 nm]]
|[[14 nanometer|12.5 nm]]
|[[Hussein I. Hanafi]], Robert H. Dennard, Yuan Taur, Nadim F. Haddad
|IBM T.J. Watson Research Center 
|<ref>{{cite article|last1=Hanafi|first1=Hussein I.|author-link=Hussein I. Hanafi|last2=Dennard|first2=Robert H.|last3=Taur|first3=Yuan|last4=Haddad|first4=Nadim F.|last5=Sun|first5=J. Y. C.|last6=Rodriguez|first6=M. D.|title=0.5 μm CMOS Device Design and Characterization|journal=ESSDERC '87: 17th European Solid State Device Research Conference|date=September 1987|pages=91–94|url=https://ieeexplore.ieee.org/document/5436921}}</ref>
|-
| 1987-12
|[[250 nanometer|250 nm]]
| ?
| Naoki Kasai, Nobuhiro Endo, Hiroshi Kitajima
|[[NEC]]
|<ref>{{cite book |last1=Kasai |first1=Naoki |title=1987 International Electron Devices Meeting |last2=Endo |first2=Nobuhiro |last3=Kitajima |first3=Hiroshi |date=December 1987 |pages=367–370 |chapter=0.25 μm CMOS technology using P<sup>+</sup>polysilicon gate PMOSFET |doi=10.1109/IEDM.1987.191433 |s2cid=9203005}}</ref>
|-
| 1988-02
|400&nbsp;nm
|[[10 nanometer|{{#expr:100/10}} nm]]
|M. Inoue, H. Kotani, T. Yamada, Hiroyuki Yamauchi
|Matsushita
|<ref name="Gealow3" /><ref>{{cite book |last1=Inoue |first1=M. |title=1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers |last2=Kotani |first2=H. |last3=Yamada |first3=T. |last4=Yamauchi |first4=Hiroyuki |last5=Fujiwara |first5=A. |last6=Matsushima |first6=J. |last7=Akamatsu |first7=Hironori |last8=Fukumoto |first8=M. |last9=Kubota |first9=M. |date=1988 |pages=246– |chapter=A 16mb Dram with an Open Bit-Line Architecture |doi=10.1109/ISSCC.1988.663712 |last10=Nakao |first10=I. |last11=Aoi |s2cid=62034618}}</ref>
|-
| 1990-12
|[[110 nanometer|100 nm]]
| ?
|[[Ghavam G. Shahidi]], [[Bijan Davari]], Yuan Taur, James D. Warnock 
|IBM T.J. Watson Research Center
|<ref>{{cite article|last1=Shahidi|first1=Ghavam G.|author1-link=Ghavam Shahidi|last2=Davari|first2=Bijan|author2-link=Bijan Davari|last3=Taur|first3=Yuan|last4=Warnock|first4=James D.|last5=Wordeman|first5=Matthew R.|last6=McFarland|first6=P. A.|last7=Mader|first7=S. R.|last8=Rodriguez|first8=M. D.|title=Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing|journal=International Technical Digest on Electron Devices|date=December 1990|pages=587–590|doi=10.1109/IEDM.1990.237130|s2cid=114249312}}</ref>
|-
|1993
|[[350 nanometer|350 nm]]
| ? 
| ?
|[[Sony]]
| rowspan="2" |<ref name="stol3">{{cite article|url=http://maltiel-consulting.com/Semiconductor_technology_memory.html|title=Memory|website=STOL (Semiconductor Technology Online)|access-date=25 June 2019|archive-date=2 November 2023|archive-url=https://web.archive.org/web/20231102131915/http://maltiel-consulting.com/Semiconductor_technology_memory.html|url-status=dead}}</ref>
|-
|1996
|[[Half-node|150 nm]]
| ?
| ?
|[[Mitsubishi Electric]]
|-
|1998
|[[180 nanometer|180 nm]]
| ?
| ?
|[[TSMC]]
|<ref>{{cite article|title=0.18-micron Technology|url=https://www.tsmc.com/english/dedicatedFoundry/technology/0.18um.htm|publisher=[[TSMC]]|access-date=30 June 2019}}</ref>
|-
| 2003-12
|[[5 nm]]
| ?
| Hitoshi Wakabayashi, Shigeharu Yamagami, Nobuyuki Ikezawa
|NEC
|<ref name="Wakabayashi2">{{cite book |last1=Wakabayashi |first1=Hitoshi |title=IEEE International Electron Devices Meeting 2003 |last2=Yamagami |first2=Shigeharu |last3=Ikezawa |first3=Nobuyuki |last4=Ogura |first4=Atsushi |last5=Narihiro |first5=Mitsuru |last6=Arai |first6=K. |last7=Ochiai |first7=Y. |last8=Takeuchi |first8=K. |last9=Yamamoto |first9=T. |date=December 2003 |isbn=0-7803-7872-5 |pages=20.7.1–20.7.3 |chapter=Sub-10-nm planar-bulk-CMOS devices using lateral junction control |doi=10.1109/IEDM.2003.1269446 |last10=Mogami |first10=T. |s2cid=2100267}}</ref><ref>{{cite article|url=http://www.thefreelibrary.com/NEC+test-produces+world's+smallest+transistor.-a0111295563|title=NEC test-produces world's smallest transistor|website=Thefreelibrary.com|access-date=7 December 2017}}</ref>
|}

== See also ==
* [[Active pixel sensor]] (CMOS sensor)
* [[Beyond CMOS]]
* [[CMOS amplifier]]
* [[Electric (software)]] – used to lay out CMOS circuits
* [[FEOL]] (front-end-of-line) – the first part of IC fabrication process
* [[Gate equivalent]]  – a technology-independent measure of circuit complexity
* [[HCMOS]] – high-speed CMOS 1982
* [[LVCMOS]]
* [[Magic (software)]] – used to lay out CMOS circuits
* [[List of MOSFET applications]]
* [[sCMOS]]
* [[Thermal oxidation]]

== References ==
{{reflist}}

== Further reading ==
{{see also|4000-series integrated circuits#Further reading|l1=List of books about 4000-series integrated circuits}}

* {{cite book |author=Baker, R. Jacob |title=CMOS: Circuit Design, Layout, and Simulation, Third Edition |url=http://CMOSedu.com |publisher=Wiley-IEEE |location= |year=2010 |page=1174 |isbn=978-0-470-88132-3 |oclc= |doi= |accessdate=}} 
* {{cite book |author1=Weste, Neil H. E. |author2=Harris, David M. |title=CMOS VLSI Design: A Circuits and Systems Perspective, Fourth Edition |url=http://CMOSVLSI.com/ |publisher=Pearson/Addison-Wesley |location=Boston |year=2010 |page=840 |isbn=978-0-321-54774-3 |oclc= |doi= |accessdate=}} 
* {{cite book |last=Veendrick |first=H. J. M. |title=Nanometer CMOS ICs: From Basics to ASICs |year=2017 |publisher=Springer |page=770 |doi=10.1007/978-3-319-47597-4 |isbn=978-3-319-47595-0}} 
* {{cite book |author=[[Carver Mead|Mead, Carver A.]] and [[Lynn Conway|Conway, Lynn]] |title=Introduction to VLSI systems |publisher=Addison-Wesley |location=Boston |year=1980 |pages= |isbn=0-201-04358-0 |oclc= |doi= |accessdate= |url-access=registration |url=https://archive.org/details/introductiontovl00mead }}

== External links ==
* [https://web.archive.org/web/20110719014039/http://tams-www.informatik.uni-hamburg.de/applets/cmos/ CMOS gate description and interactive illustrations]
* [http://lasihomesite.com/ LASI] is a "general purpose" IC layout CAD tool.  It is a free download and can be used as a layout tool for CMOS circuits.

[[Category:CMOS]]
[[Category:Electronic design]]
[[Category:Digital electronics]]
[[Category:Logic families]]
[[Category:Integrated circuits]]
[[Category:MOSFETs]]
[[Category:Arab inventions]]
[[Category:Chinese inventions]]
[[Category:Egyptian inventions]]
[[Category:South Korean inventions]]