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CMOS primarily makes use of what would otherwise be two separate circuit technologies - [[pmos transistor|pMOS]] and [[nMOS transistor|nMOS]]. To better understand this, consider an [[nMOS transistor]]. Because it can pull no higher than V<sub>DD</sub> - V<sub>t</sub> we get a degraded 1 output. Likewise with pMOS, we can pull no lower than V<sub>t</sub> - a degraded 0 output. By combining both types, we can borrow the desired characteristics from both transistors such as a strong 0 and a strong 1. | CMOS primarily makes use of what would otherwise be two separate circuit technologies - [[pmos transistor|pMOS]] and [[nMOS transistor|nMOS]]. To better understand this, consider an [[nMOS transistor]]. Because it can pull no higher than V<sub>DD</sub> - V<sub>t</sub> we get a degraded 1 output. Likewise with pMOS, we can pull no lower than V<sub>t</sub> - a degraded 0 output. By combining both types, we can borrow the desired characteristics from both transistors such as a strong 0 and a strong 1. | ||
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=== Inverter Example === | === Inverter Example === | ||
{{main|inverter}} | {{main|inverter}} | ||
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The simplest gate that can be implemented is the [[NOT gate]] which simply inverts the input. We can implement an inverter using a single nMOS and pMOS transistors. The pMOS transistor is connected to V<sub>DD</sub> while the nMOS transistor is connected to GND. When ''A'' is 0, the nMOS transistor turns OFF and the pMOS transistor turns ON. This results in ''Q'' being pulled up to 1 since the pMOS transistor will conduct V<sub>DD</sub>. Conversely, when ''A'' is 1, the nMOS transistor turns ON and the pMOS transistor turns OFF, thereby pulling ''Q'' down to GND. | The simplest gate that can be implemented is the [[NOT gate]] which simply inverts the input. We can implement an inverter using a single nMOS and pMOS transistors. The pMOS transistor is connected to V<sub>DD</sub> while the nMOS transistor is connected to GND. When ''A'' is 0, the nMOS transistor turns OFF and the pMOS transistor turns ON. This results in ''Q'' being pulled up to 1 since the pMOS transistor will conduct V<sub>DD</sub>. Conversely, when ''A'' is 1, the nMOS transistor turns ON and the pMOS transistor turns OFF, thereby pulling ''Q'' down to GND. | ||