From WikiChip
Editing cavium/thunderx2/cn9965
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 12: | Line 12: | ||
|part number 5=CN9965-2100LG4077-Y21-G | |part number 5=CN9965-2100LG4077-Y21-G | ||
|part number 6=CN9965-2000LG4077-Y21-G | |part number 6=CN9965-2000LG4077-Y21-G | ||
− | |||
|market=Server | |market=Server | ||
|first announced=May 7, 2018 | |first announced=May 7, 2018 | ||
Line 21: | Line 20: | ||
|frequency 3=2,100 MHz | |frequency 3=2,100 MHz | ||
|frequency 4=2,200 MHz | |frequency 4=2,200 MHz | ||
− | |||
− | |||
− | |||
|isa=ARMv8.1 | |isa=ARMv8.1 | ||
|isa family=ARM | |isa family=ARM | ||
Line 53: | Line 49: | ||
|l3 cache=20 MiB | |l3 cache=20 MiB | ||
|l3 break=20x1 MiB | |l3 break=20x1 MiB | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
}} | }} |
Facts about "ThunderX2 CN9965 - Cavium"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | ThunderX2 CN9965 - Cavium#pcie + |
base frequency | 1,800 MHz (1.8 GHz, 1,800,000 kHz) +, 2,000 MHz (2 GHz, 2,000,000 kHz) +, 2,100 MHz (2.1 GHz, 2,100,000 kHz) +, 2,200 MHz (2.2 GHz, 2,200,000 kHz) +, 2,300 MHz (2.3 GHz, 2,300,000 kHz) +, 2,400 MHz (2.4 GHz, 2,400,000 kHz) + and 2,500 MHz (2.5 GHz, 2,500,000 kHz) + |
core count | 20 + |
designer | Cavium + |
family | ThunderX2 + |
first announced | May 7, 2018 + |
first launched | May 7, 2018 + |
full page name | cavium/thunderx2/cn9965 + |
has ecc memory support | true + |
instance of | microprocessor + |
isa | ARMv8.1 + |
isa family | ARM + |
l1$ size | 1,280 KiB (1,310,720 B, 1.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 640 KiB (655,360 B, 0.625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 640 KiB (655,360 B, 0.625 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 5 MiB (5,120 KiB, 5,242,880 B, 0.00488 GiB) + |
l3$ size | 20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) + |
ldate | May 7, 2018 + |
manufacturer | TSMC + |
market segment | Server + |
max cpu count | 2 + |
max memory | 2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) + |
max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
max memory channels | 6 + |
max sata ports | 2 + |
max usb ports | 2 + |
microarchitecture | Vulcan + |
model number | CN9965 + |
name | ThunderX2 CN9965 + |
package | FCLGA-4077 + |
part number | CN9965-2500LG4077-Y21-G +, CN9965-2400LG4077-Y21-G +, CN9965-2300LG4077-Y21-G +, CN9965-2200LG4077-Y21-G +, CN9965-2100LG4077-Y21-G +, CN9965-2000LG4077-Y21-G + and CN9965-1800LG4077-Y21-G + |
process | 16 nm (0.016 μm, 1.6e-5 mm) + |
smp max ways | 2 + |
supported memory type | DDR4-2666 + |
technology | CMOS + |
thread count | 40 + |
word size | 64 bit (8 octets, 16 nibbles) + |