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{{cavium title|CN5840-900 EXP}} | {{cavium title|CN5840-900 EXP}} | ||
− | {{ | + | {{mpu |
| name = Cavium CN5840-900 EXP | | name = Cavium CN5840-900 EXP | ||
| no image = | | no image = | ||
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| model number = CN5840-900 EXP | | model number = CN5840-900 EXP | ||
| part number = CN5840-900BG1521-EXP | | part number = CN5840-900BG1521-EXP | ||
+ | | part number 1 = | ||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
− | |||
| market = Network | | market = Network | ||
| first announced = October 9, 2006 | | first announced = October 9, 2006 | ||
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| tambient max = | | tambient max = | ||
− | |package | + | | packaging = Yes |
+ | | package 0 = FCBGA-1521 | ||
+ | | package 0 type = FCBGA | ||
+ | | package 0 pins = 1521 | ||
+ | | package 0 pitch = | ||
+ | | package 0 width = | ||
+ | | package 0 length = | ||
+ | | package 0 height = | ||
+ | | socket 0 = BGA-1521 | ||
+ | | socket 0 type = BGA | ||
}} | }} | ||
'''CN5840-900 EXP''' is a {{arch|64}} [[octa-core]] [[MIPS]] network microprocessor designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates eight {{cavium|cnMIPS|l=arch}} cores, operates at 900 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of various software such as [[RegEx]], compression/decompression, and TCP acceleration. | '''CN5840-900 EXP''' is a {{arch|64}} [[octa-core]] [[MIPS]] network microprocessor designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates eight {{cavium|cnMIPS|l=arch}} cores, operates at 900 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of various software such as [[RegEx]], compression/decompression, and TCP acceleration. |
Facts about "CN5840-900 EXP - Cavium"