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{{cavium title|CN3630-500 SCP}} | {{cavium title|CN3630-500 SCP}} | ||
− | {{ | + | {{mpu |
| name = Cavium CN3630-500 SCP | | name = Cavium CN3630-500 SCP | ||
| no image = | | no image = | ||
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| model number = CN3630-500 SCP | | model number = CN3630-500 SCP | ||
| part number = CN3630-500BG1521-SCP | | part number = CN3630-500BG1521-SCP | ||
+ | | part number 1 = | ||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
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| market = Networking | | market = Networking | ||
| first announced = August, 2005 | | first announced = August, 2005 | ||
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| tambient max = | | tambient max = | ||
− | |package | + | | packaging = Yes |
+ | | package 0 = BGA-1521 | ||
+ | | package 0 type = BGA | ||
+ | | package 0 pins = 1521 | ||
+ | | package 0 pitch = | ||
+ | | package 0 width = | ||
+ | | package 0 length = | ||
+ | | package 0 height = | ||
+ | | socket 0 = | ||
+ | | socket 0 type = | ||
}} | }} | ||
The '''CN3630-500 SCP''' is a {{arch|64}} [[quad-core]] [[MIPS]] secure network communication [[microprocessor]] (SNP) designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates four {{cavium|cnMIPS|l=arch}} cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and encryption. This MPU supports up to 16 GiB of DDR2-800 ECC memory. | The '''CN3630-500 SCP''' is a {{arch|64}} [[quad-core]] [[MIPS]] secure network communication [[microprocessor]] (SNP) designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates four {{cavium|cnMIPS|l=arch}} cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and encryption. This MPU supports up to 16 GiB of DDR2-800 ECC memory. |
Facts about "CN3630-500 SCP - Cavium"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | CN3630-500 SCP - Cavium#package + |
base frequency | 500 MHz (0.5 GHz, 500,000 kHz) + |
core count | 4 + |
core name | cnMIPS + |
designer | Cavium + |
family | OCTEON + |
first announced | August 2005 + |
first launched | August 2005 + |
full page name | cavium/octeon/cn3630-500bg1521-scp + |
has ecc memory support | true + |
has hardware accelerators for cryptography | true + |
has hardware accelerators for network quality of service processing | true + |
has hardware accelerators for tcp packet processing | true + |
instance of | microprocessor + |
isa | MIPS64 + |
isa family | MIPS + |
l1$ size | 160 KiB (163,840 B, 0.156 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1i$ description | 64-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
ldate | August 2005 + |
main image | + |
manufacturer | TSMC + |
market segment | Networking + |
max cpu count | 1 + |
max memory | 16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) + |
max memory bandwidth | 5.96 GiB/s (6,103.04 MiB/s, 6.4 GB/s, 6,399.501 MB/s, 0.00582 TiB/s, 0.0064 TB/s) + |
max memory channels | 1 + |
microarchitecture | cnMIPS + |
model number | CN3630-500 SCP + |
name | Cavium CN3630-500 SCP + |
package | FCBGA-1521 + |
part number | CN3630-500BG1521-SCP + |
process | 130 nm (0.13 μm, 1.3e-4 mm) + |
series | CN3600 + |
smp max ways | 1 + |
supported memory type | DDR2-800 + |
technology | CMOS + |
thread count | 4 + |
word size | 64 bit (8 octets, 16 nibbles) + |