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{{cavium title|CN3005-300 SCP}} | {{cavium title|CN3005-300 SCP}} | ||
− | {{ | + | {{mpu |
| name = Cavium CN3005-300 SCP | | name = Cavium CN3005-300 SCP | ||
− | | no image = | + | | no image = cn3005-15.png |
− | | image = | + | | image = |
| image size = | | image size = | ||
| caption = | | caption = | ||
| designer = Cavium | | designer = Cavium | ||
| manufacturer = TSMC | | manufacturer = TSMC | ||
− | | model number = CN3005 | + | | model number = CN3005 |
| part number = CN3005-300BG350-SCP | | part number = CN3005-300BG350-SCP | ||
+ | | part number 1 = | ||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
− | |||
| market = Embedded | | market = Embedded | ||
| first announced = January 30, 2006 | | first announced = January 30, 2006 | ||
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| max memory addr = | | max memory addr = | ||
− | + | | electrical = Yes | |
| power = 2 W | | power = 2 W | ||
| v core = | | v core = | ||
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| socket 0 type = | | socket 0 type = | ||
}} | }} | ||
− | The '''CN3005-300 SCP''' is a {{arch|64}} [[single-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in early [[2006]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 300 MHz and dissipates 2 Watts. This processors includes a number of hardware security communication accelerators including units for encryption, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 memory. | + | The '''CN3005-300 SCP''' is a {{arch|64}} [[single-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in early [[2006]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 300 MHz and dissipates 2 Watts. This processors includes a number of hardware security communication accelerators including units for encryption, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory. |
== Cache == | == Cache == | ||
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{{memory controller | {{memory controller | ||
|type=DDR2-533 | |type=DDR2-533 | ||
− | |ecc= | + | |ecc=Yes |
|max mem=2 GiB | |max mem=2 GiB | ||
|controllers=1 | |controllers=1 | ||
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== Expansions == | == Expansions == | ||
{{expansions | {{expansions | ||
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|usb revision=2.0 | |usb revision=2.0 | ||
|usb ports=1 | |usb ports=1 | ||
− | + | |uart=2 | |
− | |||
− | |uart | ||
− | |||
|gp io=Yes | |gp io=Yes | ||
}} | }} | ||
== Networking == | == Networking == | ||
− | + | * 1x RGMII/MII | |
− | + | * 1x GMII/MII | |
− | + | * 32-bit, 66 MHz PCI host or slave | |
− | + | * TDM/PCM interface for glueless VoIP support | |
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− | == | + | == Features == |
− | * | + | Hardware acceleration units: |
+ | * Hardware implementation for common security algorithms: | ||
+ | ** DES, 3DES, AES (up to 256 bit), SHA1, SHA-2 up to SHA-512, RSA, DH | ||
+ | * QoS | ||
+ | * TCP Acceleration |
Facts about "CN3005-300 SCP - Cavium"
base frequency | 300 MHz (0.3 GHz, 300,000 kHz) + |
core count | 1 + |
core name | cnMIPS + |
designer | Cavium + |
family | OCTEON + |
first announced | January 30, 2006 + |
first launched | May 1, 2006 + |
full page name | cavium/octeon/cn3005-300bg350-scp + |
has ecc memory support | false + |
has hardware accelerators for cryptography | true + |
has hardware accelerators for network quality of service processing | true + |
has hardware accelerators for tcp packet processing | true + |
instance of | microprocessor + |
isa | MIPS64 + |
isa family | MIPS + |
l1$ size | 24 KiB (24,576 B, 0.0234 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l2$ description | 2-way set associative + |
l2$ size | 0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + |
ldate | May 1, 2006 + |
main image | + |
manufacturer | TSMC + |
market segment | Embedded + |
max cpu count | 1 + |
max memory | 2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) + |
max memory bandwidth | 0.993 GiB/s (1,017 MiB/s, 1.066 GB/s, 1,066.402 MB/s, 9.698868e-4 TiB/s, 0.00107 TB/s) + |
max memory channels | 1 + |
microarchitecture | cnMIPS + |
model number | CN3005-300 SCP + |
name | Cavium CN3005-300 SCP + |
part number | CN3005-300BG350-SCP + |
power dissipation | 2 W (2,000 mW, 0.00268 hp, 0.002 kW) + |
process | 130 nm (0.13 μm, 1.3e-4 mm) + |
release price | $ 19.00 (€ 17.10, £ 15.39, ¥ 1,963.27) + |
series | CN3000 + |
smp max ways | 1 + |
supported memory type | DDR2-533 + |
technology | CMOS + |
thread count | 1 + |
word size | 64 bit (8 octets, 16 nibbles) + |