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'''Cortex-X1''' (codename '''Hera''') is a performance-enhanced version of the {{armh|Cortex-A78|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[Arm]] for the mobile market. The Cortex-X1 was designed by Arm's Austin, Texas team. This microarchitecture is designed as a synthesizable [[IP core]] and is licensed to other semiconductor companies to be implemented in their own chips. | '''Cortex-X1''' (codename '''Hera''') is a performance-enhanced version of the {{armh|Cortex-A78|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[Arm]] for the mobile market. The Cortex-X1 was designed by Arm's Austin, Texas team. This microarchitecture is designed as a synthesizable [[IP core]] and is licensed to other semiconductor companies to be implemented in their own chips. | ||
− | The Cortex-X1, which implements the {{arm|ARMv8.2}} ISA, is a higher performance core that is designed to be combined with the {{\\|Cortex-A78}} in a {{armh|DynamIQ big.LITTLE}} | + | The Cortex-X1, which implements the {{arm|ARMv8.2}} ISA, is a higher performance core that is designed to be combined with the {{\\|Cortex-A78}} in a {{armh|DynamIQ big.LITTLE}} in order to provide even higher single-thread performance. This core, along with the {{\\|Cortex-A78}}, are often combined with a number of low(er) power cores (e.g. {{\\|Cortex-A55}}) in order to achieve better energy/performance. |
== Process Technology == | == Process Technology == |
Facts about "Cortex-X1 - Microarchitectures - ARM"
codename | Cortex-X1 + |
core count | 1 +, 2 +, 4 +, 6 + and 8 + |
designer | ARM Holdings + |
first launched | May 26, 2020 + |
full page name | arm holdings/microarchitectures/cortex-x1 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.2 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Cortex-X1 + |
pipeline stages | 13 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) + |