From WikiChip
Editing arm holdings/microarchitectures/cortex-a8
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 39: | Line 39: | ||
|} | |} | ||
− | One can specify {{arm|NEON}} support using the <code>-mfpu=neon</code> option. Note that GCC will not generate floating-point operations for auto-vectorization constructs because | + | One can specify {{arm|NEON}} support using the <code>-mfpu=neon</code> option. Note that GCC will not generate floating-point operations for auto-vectorization constructs because NEON is not fully [[IEEE 754]]-compliant. It's possible to use <code>-funsafe-math-optimizations</code> to circumvent that behavior. |
== Architecture == | == Architecture == | ||
Line 109: | Line 109: | ||
== Die == | == Die == | ||
− | * [[65 nm process]] | + | * [[65 nm process]] |
− | * Up to | + | * Up to 1 GHz |
− | * 4 mm² ( | + | * 4 mm² (core only, no NEON, L2 cache, and embedded trace) |
− | |||
− | |||
* <= 300 mW | * <= 300 mW | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− |
Facts about "Cortex-A8 - Microarchitectures - ARM"
codename | Cortex-A8 + |
designer | ARM Holdings + |
first launched | October 5, 2005 + |
full page name | arm holdings/microarchitectures/cortex-a8 + |
instance of | microarchitecture + |
instruction set architecture | ARMv7 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Cortex-A8 + |
pipeline stages | 13 + |
process | 65 nm (0.065 μm, 6.5e-5 mm) + and 45 nm (0.045 μm, 4.5e-5 mm) + |