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|manufacturer=TSMC | |manufacturer=TSMC | ||
|introduction=February 11, 2014 | |introduction=February 11, 2014 | ||
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|predecessor=Cortex-A12 | |predecessor=Cortex-A12 | ||
|predecessor link=arm_holdings/microarchitectures/cortex-a12 | |predecessor link=arm_holdings/microarchitectures/cortex-a12 | ||
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=== Memory Hierarchy === | === Memory Hierarchy === | ||
{{empty section}} | {{empty section}} | ||
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== Die == | == Die == | ||
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* TSMC [[28 nm process]] | * TSMC [[28 nm process]] | ||
* 89 mm² die size | * 89 mm² die size | ||
| − | * Quad-core {{ | + | * Quad-core {{armh|Cortex-A7|l=arch}} |
** ~0.48 mm² per core | ** ~0.48 mm² per core | ||
| − | * Quad-core Cortex-A17 + 2 MiB L2 | + | * Quad-core {{armh|Cortex-A17|l=arch}} + 2 MiB L2 |
** ~1.93 mm² per core | ** ~1.93 mm² per core | ||
** ~3.93 mm² for 2 MiB L2 | ** ~3.93 mm² for 2 MiB L2 | ||
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(small quad-core is unlabeled below the big core cluster) | (small quad-core is unlabeled below the big core cluster) | ||
:[[File:mt6595 die shot.png|600px]] | :[[File:mt6595 die shot.png|600px]] | ||
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Facts about "Cortex-A17 - Microarchitectures - ARM"
| codename | Cortex-A17 + |
| designer | ARM Holdings + |
| first launched | February 11, 2014 + |
| full page name | arm holdings/microarchitectures/cortex-a17 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv7 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Cortex-A17 + |