From WikiChip
Editing amd/ryzen 5
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 12: | Line 12: | ||
| arch = mid-range performance x86 processors | | arch = mid-range performance x86 processors | ||
| isa = x86-64 | | isa = x86-64 | ||
− | | microarch = Zen | + | | microarch = Zen |
| word = 64 bit | | word = 64 bit | ||
− | | proc = | + | | proc = 14 nm |
| tech = CMOS | | tech = CMOS | ||
− | | clock min = 3, | + | | clock min = 3,200 MHz |
− | | clock max = | + | | clock max = 3,600 MHz |
| package = µOPGA-1331 | | package = µOPGA-1331 | ||
| socket = Socket AM4 | | socket = Socket AM4 | ||
Line 29: | Line 29: | ||
'''Ryzen 5''' (pronounced ''Rye-Zen Five'') is a family of mid-range performance {{arch|64}} [[quad-core|quad]] and [[hexa-core]]s [[x86]] microprocessors introduced by [[AMD]] in March of [[2017]]. Ryzen 5 is based on the {{amd|Zen|l=arch}} microarchitecture and is manufactured on [[globalfoundries|GF's]] [[14 nm process]]. Ryzen 5 is marketed toward the mid-range performance market. The Ryzen 5 is positioned against Intel's mid-range mainstream {{intel|Core i5}} processors, offering competitive performance at lower prices. | '''Ryzen 5''' (pronounced ''Rye-Zen Five'') is a family of mid-range performance {{arch|64}} [[quad-core|quad]] and [[hexa-core]]s [[x86]] microprocessors introduced by [[AMD]] in March of [[2017]]. Ryzen 5 is based on the {{amd|Zen|l=arch}} microarchitecture and is manufactured on [[globalfoundries|GF's]] [[14 nm process]]. Ryzen 5 is marketed toward the mid-range performance market. The Ryzen 5 is positioned against Intel's mid-range mainstream {{intel|Core i5}} processors, offering competitive performance at lower prices. | ||
== Overview == | == Overview == | ||
− | Introduced in April 2017, the Ryzen 5 family is aimed at mid-range performance desktop and sport either [[4 cores|4]] or [[6 cores|6]] cores. The Ryzen 5 is situated under the {{amd|Ryzen 7}} family, offering all of the features but | + | Introduced in April 2017, the Ryzen 5 family is aimed at mid-range performance desktop and sport either [[4 cores|4]] or [[6 cores|6]] cores. The Ryzen 5 is situated under the {{amd|Ryzen 7}} family, offering all of the features but less cores. |
− | |||
== Models == | == Models == | ||
Line 38: | Line 37: | ||
Announced in May and introduced in April 2017, the Ryzen 5 processors are mid-range performance processors with [[4 cores|4]] to [[6 cores|6]] cores and multi-threading support. All models have: | Announced in May and introduced in April 2017, the Ryzen 5 processors are mid-range performance processors with [[4 cores|4]] to [[6 cores|6]] cores and multi-threading support. All models have: | ||
− | * '''Mem:''' Up to | + | * '''Mem:''' Up to 64 MiB of dual-channel 2666 MT/s DDR4 memory |
* '''TDP:''' 65 W / 95 W | * '''TDP:''' 65 W / 95 W | ||
* '''ISA:''' Everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}} | * '''ISA:''' Everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}} | ||
Line 86: | Line 85: | ||
Zen-based mobile Ryzen 5 processors were introduced in late 2017. Those processors feature [[4 cores]] and multi-threading support as well as an integrated graphics processor. All models have: | Zen-based mobile Ryzen 5 processors were introduced in late 2017. Those processors feature [[4 cores]] and multi-threading support as well as an integrated graphics processor. All models have: | ||
− | * '''Mem:''' Up to 32 | + | * '''Mem:''' Up to 32 MiB of dual-channel 2400 MT/s DDR4 memory |
* '''TDP:''' 15 W | * '''TDP:''' 15 W | ||
* '''ISA:''' Everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}} | * '''ISA:''' Everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}} | ||
Line 99: | Line 98: | ||
--> | --> | ||
{{comp table start}} | {{comp table start}} | ||
− | <table class="comptable sortable | + | <table class="comptable sortable tc4 tc5"> |
− | {{comp table header|main| | + | {{comp table header|main|12:List of Zen-based Ryzen 5 Mobile Processors}} |
− | {{comp table header|main| | + | {{comp table header|main|8:Processor|2:Integrated Graphics}} |
− | {{comp table header|cols|Launched|Cores|Threads|L3$|TDP|Frequency|Turbo|Name|Turbo}} | + | {{comp table header|cols|Price|Launched|Cores|Threads|L3$|TDP|Frequency|Turbo|Name|Turbo}} |
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microprocessor family::Ryzen 5]] [[microarchitecture::Zen]] [[market segment::Mobile]] | {{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microprocessor family::Ryzen 5]] [[microarchitecture::Zen]] [[market segment::Mobile]] | ||
|?full page name | |?full page name | ||
|?model number | |?model number | ||
+ | |?release price | ||
|?first launched | |?first launched | ||
|?core count | |?core count | ||
Line 117: | Line 117: | ||
|format=template | |format=template | ||
|template=proc table 3 | |template=proc table 3 | ||
− | |userparam= | + | |userparam=12 |
|mainlabel=- | |mainlabel=- | ||
}} | }} | ||
Line 127: | Line 127: | ||
{{see also|amd/microarchitectures/zen+|l1=Zen+ µarch}} | {{see also|amd/microarchitectures/zen+|l1=Zen+ µarch}} | ||
==== Desktop ==== | ==== Desktop ==== | ||
− | Introduced in April 2018, Zen+ based Ryzen 5 processors provide a small [[IPC]] | + | Introduced in April 2018, Zen+ based Ryzen 5 processors provide a small [[IPC]] imprvement through various memory and cache ennhancements as well as a modest clock frequency imprvement over their predecessors. Additionally, all models have: |
− | * '''Mem:''' Up to 64 | + | * '''Mem:''' Up to 64 MiB of dual-channel 2933 MT/s DDR4 memory |
* '''TDP:''' 65 W / 95 W (XFR models) | * '''TDP:''' 65 W / 95 W (XFR models) | ||
* '''ISA:''' Everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}} | * '''ISA:''' Everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}} | ||
Line 144: | Line 144: | ||
{{comp table start}} | {{comp table start}} | ||
<table class="comptable sortable tc4 tc5 tc15 tc16 tc17"> | <table class="comptable sortable tc4 tc5 tc15 tc16 tc17"> | ||
− | {{comp table header|main|11:List of Zen+ based Ryzen 5 Desktop Processors}} | + | {{comp table header|main|11:List of Zen+-based Ryzen 5 Desktop Processors}} |
+ | {{comp table header|main|9:Processor}} | ||
{{comp table header 1|cols=Price, Launched, Cores, Threads, TDP, L2$, L3$, Frequency, Max Turbo}} | {{comp table header 1|cols=Price, Launched, Cores, Threads, TDP, L2$, L3$, Frequency, Max Turbo}} | ||
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microprocessor family::Ryzen 5]] [[microarchitecture::Zen+]][[market segment::Desktop]] | {{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microprocessor family::Ryzen 5]] [[microarchitecture::Zen+]][[market segment::Desktop]] | ||
Line 157: | Line 158: | ||
|?l3$ size | |?l3$ size | ||
|?base frequency#GHz | |?base frequency#GHz | ||
− | |?turbo frequency#GHz | + | |?turbo frequency (1 core)#GHz |
|format=template | |format=template | ||
|template=proc table 3 | |template=proc table 3 | ||
Line 164: | Line 165: | ||
}} | }} | ||
{{comp table count|ask=[[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microprocessor family::Ryzen 5]] [[microarchitecture::Zen+]][[market segment::Desktop]]}} | {{comp table count|ask=[[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microprocessor family::Ryzen 5]] [[microarchitecture::Zen+]][[market segment::Desktop]]}} | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
</table> | </table> | ||
{{comp table end}} | {{comp table end}} | ||
Line 295: | Line 171: | ||
* AMD | * AMD | ||
** {{amd|Zen}} | ** {{amd|Zen}} | ||
− | ** {{amd| | + | ** {{amd|Ryzen 7}} |
− | |||
** {{amd|Ryzen 3}} | ** {{amd|Ryzen 3}} | ||
− | |||
− | |||
* Intel | * Intel | ||
** {{intel|Core i5}} | ** {{intel|Core i5}} | ||
** {{intel|Skylake}}, {{intel|Kaby Lake}} | ** {{intel|Skylake}}, {{intel|Kaby Lake}} |
Facts about "Ryzen 5 - AMD"
designer | AMD + |
first announced | March 16, 2017 + |
first launched | April 11, 2017 + |
full page name | amd/ryzen 5 + |
instance of | microprocessor family + |
instruction set architecture | x86-64 + |
main designer | AMD + |
manufacturer | GlobalFoundries + |
microarchitecture | Zen 2 + |
name | AMD Ryzen 5 + |
package | µOPGA-1331 + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + |
socket | Socket AM4 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |