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| | |market=Server | | |market=Server |
| | |microarch=Zen | | |microarch=Zen |
| − | |microarch 2=Zen 2
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| − | |microarch 3=Zen 3
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| | |tdp=120 W | | |tdp=120 W |
| | |tdp 2=155 W | | |tdp 2=155 W |
| | |tdp 3=180 W | | |tdp 3=180 W |
| − | |package name=SP3 | + | |package name=FCLGA-4094 |
| − | |package name 2=FCLGA-4094
| + | |package type=Organic Flip-Chip Land Grid Array |
| − | |package type=FC-OLGA | |
| | |package contacts=4094 | | |package contacts=4094 |
| − | |package dimension=75.40 mm | + | |package dimension=58.5 mm |
| − | |package dimension 2=58.50 mm | + | |package dimension 2=75.4 mm |
| − | |package dimension 3=6.26 mm
| + | |package pitch=1.00 mm |
| − | |package pitch=0.87 mm | + | |socket name=Socket SP3 |
| − | |package pitch 2=1.00 mm
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| − | |socket type=SM-LGA
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| − | |socket name=SP3 | |
| | |socket name 2=LGA-4094 | | |socket name 2=LGA-4094 |
| − | |predecessor=Socket G34 | + | |socket type=LGA |
| − | |predecessor link=amd/packages/socket g34
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| − | |successor=Socket SP5
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| − | |successor link=amd/packages/socket sp5
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| − | |contemporary=Socket TR4
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| − | |contemporary link=amd/packages/socket tr4
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| − | |contemporary 2=Socket sTRX4
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| − | |contemporary 2 link=amd/packages/socket strx4
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| − | |contemporary 3=Socket sWRX8
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| − | |contemporary 3 link=amd/packages/socket swrx8
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| | }} | | }} |
| − | '''Socket SP3''' is a microprocessor socket designed by [[AMD]] for the first three generations of their {{amd|EPYC}} family of high performance server processors. It supports eight channels of [[DDR4]] memory and eight 16-lane PCIe I/O links. Socket SP3 succeeded {{\\|Socket G34}} and was superseded by {{\\|Socket SP5}}. | + | '''Socket SP3''' is a [[land grid array]] microprocessor [[socket]] designed by AMD for their {{amd|EPYC}} family supported by the {{amd|Zen|l=arch}} microarchitectures. This socket is designed for ICs with a 4094-contact FCLGA packages. |
| − | | |
| − | Three other sockets were derived from, and are mechanically identical to Socket SP3 but differ electrically: {{\\|Socket TR4}} a.k.a. Socket SP3r2 for first and second generation, and {{\\|Socket sTRX4}} for third generation {{amd|Ryzen Threadripper}} high end desktop processors. These infrastructures support only four memory channels and {{abbr|UDIMM}}s instead of {{abbr|RDIMM}}s. Processors for these sockets are not compatible with Socket SP3 or vice versa. {{\\|Socket sWRX8}} is designated for Ryzen Threadripper workstation processors which support eight memory channels and both UDIMM and RDIMM types.
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| − | | |
| − | For mainstream desktop processors AMD developed {{\\|Socket AM4}}.
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| − | Contemporary mobile and embedded processors use the {{abbr|BGA}}
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| − | packages {{\\|FT5}}, {{\\|FP5}}, {{\\|FP6}}, and {{\\|SP4}}. | |
| | | | |
| | == Overview == | | == Overview == |
| − | Socket SP3 is a zero insertion force, screw actuated, [[wikipedia:Surface-mount technology|surface-mount]] [[land grid array]] socket for use with a 4094-contact, 1.00 mm × 0.87 mm interstitial pitch, organic land grid array CPU package.
| + | SP3 is a socket specifically designed by AMD for their {{amd|EPYC}} family of server processors and is supported by processors based on the {{amd|Zen|l=arch}} microarchitectures. Physically, the package is identical to the one used for {{amd|Socket TR4}} for their {{amd|Threadripper}} processors, however, the features are very different. |
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| − | It supports eight channels of 72-bit [[DDR4]] memory with up to 2 DIMMs per channel, eight 16-lane PCIe Gen 3/4 I/O links, three or four of which are repurposed as inter-socket links on dual socket systems, four USB 3.1 Gen 1 ports, and up to 32 SATA Gen 3 ports.
| + | :[[File:sp3-details.png|1000px]] |
| | | | |
| − | This compares to four [[DDR3]] channels and five [[HyperTransport]] links on its predecessor {{\\|Socket G34}}, while the newer {{\\|Socket SP5}} supports 12 channels of [[DDR5]] memory, eight PCIe Gen 5 links, and four USB 3.2 Gen 1 ports. ({{\\|SP4|SP4 and SP4r2}} are [[ball grid array]] packages of {{amd|epyc embedded#3000 Series (Zen)|EPYC 3000}} embedded processors.)
| + | == Package == |
| − | | + | <gallery widths=500px heights=400px> |
| − | The following AMD processor families use Socket SP3:
| + | File:amd naples (front).png|FCLGA-4094, package front |
| − | {| class="wikitable"
| + | File:amd naples (back).png|FCLGA-4094, package back |
| − | ! || CPU Family || Microarch. || Process || Products
| + | </gallery> |
| − | |-
| |
| − | |Type 0
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| − | |{{amd|CPUID#Family 23 (17h)|Family 17h}} Models 00h–0Fh
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| − | |{{amd|Zen|l=arch}}
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| − | |[[14 nm]]
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| − | |EPYC 7001 "{{amd|Naples|l=core}}" (Model 01h), EPYC Embedded 7001
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| − | |-
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| − | |Type 1
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| − | |Family 17h Models 30h–3Fh
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| − | |{{amd|Zen 2|l=arch}}
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| − | |[[7 nm]]
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| − | |EPYC 7002 "{{amd|Rome|l=core}}" (Model 31h), EPYC Embedded 7002
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| − | |-
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| − | |Type 2
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| − | |{{amd|CPUID#Family 25 (19h)|Family 19h}} Models 00h–0Fh
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| − | |{{amd|Zen 3|l=arch}}
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| − | |[[7 nm]]
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| − | |EPYC 7003 "{{amd|Milan|l=core}}" (Model 01h)
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| − | |}
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| − | | |
| − | Codenames of AMD SP3 reference platforms ({{abbr|CRB}}s) are "Diesel", "Ethanol", "Daytona", and "Ethanol-X".
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| − | | |
| − | Specifications of a dual socket EPYC blade motherboard and collaterals including BOM, CAD file, CPLD programming data, Eagle layout, and schematic were published by the [https://opencompute.org Open Compute Project] under Project Olympus AMD EPYC, specifically the US1-EPYC implementation by [[wikipedia:Quanta Computer|Quanta]].
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| − | | |
| − | == Package Description ==
| |
| − | The SP3 CPU package is lidded, has a 58.50 mm × 75.40 mm organic substrate with [[flip chip]] die attachment, 4094 nickel and gold plated land pads, and weighs up to 140 g.<!--AMD-55260--> It leaves AMD's {{abbr|OSAT}} partner in a shipping tray with a carrier frame pre-installed. The carrier frame is a part of the package loading mechanism and remains on the package in the socket.
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| − | | |
| − | The package substrate has six keying notches along the short edges preventing it from being inserted 180 degrees rotated into the carrier frame or socket, or in an incompatible socket with mismatching keying features. Four additional positions are reserved for future models. However all sockets SP3, TR4, sTRX4, and sWRX8, and all processors for these sockets have the same keying. It is worth noting that these processors are also electrically keyed by pin [[#CORETYPE|CORETYPE]], [[#SP3R1|SP3R1]], and [[#SP3R2|SP3R2]], and SP3 motherboards are not supposed to power up the socket if a TR4 or sTRX4 processor is installed.<!--AMD-55414 Sec 11.5.3--> To boot the processor compatible firmware is also required. A triangular symbol on both sides of the substrate marks the location of pin A1, with corresponding markings on the socket.
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| − | | |
| − | The lid a.k.a. integrated heat spreader of Type-0 processors has an internal support bar bisecting their four dies. SP3 packages place [[wikipedia:Decoupling capacitor|decoupling capacitors]] under the lid around the chiplet periphery on the top side, and in two windows in the pad grid on the bottom side.
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| − | | |
| − | All SP3 packages are [[multi-chip package|multi-chip modules]]. Type-0 packages integrate four identical "Zeppelin" rev. ZP-B2 dies, each containing eight CPU cores and implementing one quarter of the processor's memory and I/O interfaces. AMD used the same dies in various revisions for first generation EPYC server and embedded processors, and the first two generations of Ryzen Threadripper and Ryzen desktop processors without {{abbr|iGPU}}; see {{amd|CPUID#Family 23 (17h)|CPU Family 17h}}.
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| − | Customized, single-ended, 4:1 {{abbr|SerDes}} links routed on
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| − | two package layers, 32 lanes wide in each direction, connect the dies.
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| − | AMD chose not to route these signals on a 2.5D interposer or [[EMIB]]
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| − | for reasons of product flexibility and reach.<!--Burd2018,
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| − | Naffziger2020--> The SerDes run at {{abbr|FCLK|Infinity Fabric clock}}
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| − | so for instance a 1.33 GHz FCLK coupled to the bus clock of
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| − | DDR4-2666 SDRAM gives a raw data rate of 5.33 GT/s per lane or
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| − | 21.33 GB/s in each direction.<!--Beck2018, Naffziger2020, EPYC
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| − | Tech Day 2017-06-20--> The following diagram illustrates the routing
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| − | of high speed signals between the dies and the package contacts. Four
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| − | package layers were used for these signals: Layer A, B, or both for | |
| − | the GMI links, C & D for the xGMI and I/O links, and all four layers
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| − | (one per channel) for the memory interfaces.<!--Burd2018-->
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| − | | |
| − | [[file:Socket SP3 Type-0 routing.svg|left]] Type-0 package top view, not to scale. {{abbr|CAKE}}s extend the Data Fabric transport layer off-chip by connecting to a CAKE in another die. Their {{abbr|PCS}} interface drives a {{abbr|GMI}} (same socket) or {{abbr|xGMI}} (different socket) physical link. Each die has two 16-lane multi-function I/O interfaces. Type A supports the PCIe, SATA, and XGBE protocols, Type B only PCIe. CAKE2/CAKE3 and the I/O controllers share a 16-lane [[wikipedia:Physical_layer#PHY|PHY]] group. {{abbr|IF:CS}}0 and CS1 are the Data Fabric's interface to the memory controllers, {{abbr|UMC}}0 and UMC1 respectively. Not shown are the Control Fabric interfaces which use {{abbr|TWIX}} (same socket) or {{abbr|WAFL}} (different socket) physical links, USB signals (USB0 group from die 0, USB1 from die 1), and low speed busses. For details and the on-chip topology see AMD {{amd|Infinity Fabric}}. {{clear}}
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| − | | |
| − | Type-1/2 packages integrate one central I/O die and 2, 4, 6, or 8 identical Core Complex Dies which contain eight CPU cores each, populated in order CCD2/CCD4, CCD0/CCD6, and CCD1/CCD7. This silicon is "Starship" rev. SSP-B0 ({{amd|CPUID#Family 23 (17h)|CPU Family 17h}})<!--AMD-56323-0.78--> and "Genesis" GN-B1 ({{amd|CPUID#Family 25 (19h)|19h}}).<!--AMD-56683-1.04--> AMD used the same chips, possibly different revisions, for second and third generation EPYC server and embedded processors, and Ryzen Threadripper {{abbr|HEDT}} and workstation processors.
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| − | | |
| − | [[file:Socket SP3 Type-1 routing.svg|left]] Type-1/2 package top view, not to scale. Eight {{abbr|IF:CCM}} blocks extend the Data Fabric on the IOD to the CCDs, each driving a GMI2 physical link routed on two package layers. SSP-B0 CCDs contain two {{abbr|CCX}}s with 16 MiB L3 cache each, the GMI2 port and its die bumps are located in the center to reduce memory latency from the L3 cache.<!--Naffziger2020--> GN-B1 CCDs contain one CCX with 32 MiB L3 cache, the GMI2 signals are routed to the chip edge. These are serial, single-ended links with 31 transmit (to IOD) and 39 receive lanes, one clock gating lane per direction, and a differential pair of clock lanes. GMI2 uses 10:1 SerDes running at FCLK, so for instance a 1.46 GHz FCLK (~ DDR4-2933) gives a raw data rate of 14.6 GT/s per lane or 71.2 GB/s per link from IOD to CCD. Not shown are eight TWIX ports extending the Control Fabric to the CCDs, these links run on four data and two clock lanes, as well as WAFL links, USB signals, and low speed busses. The "Rome" package actually has 20 layers (9-2-9) in total. <!--AMD-55803 PPR SSP-B0, Singh2020, Naffziger2020--> For details and the IOD internal topology see AMD {{amd|Infinity Fabric}}. {{clear}}
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| − | | |
| − | Socket SP3 supports eight 72-bit DDR4 memory channels A-H with up to 2 {{abbr|DIMM}}s per channel. The DIMMs are placed in order A-D and E-H parallel to the socket's broad sides. This also applies to Socket sTRX4 (where only the four channels A, D, E, and H are available), Socket sWRX8 (with a maximum of one DIMM per channel), as well as SP3 and sTRX4 motherboards supporting only one DIMM per channel as a trade-off between performance (as point-to-point connections improve signal integrity and permit higher data rates), board size and memory capacity.
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| − | | |
| − | Furthermore Socket SP3 supports eight 16-lane multi-function I/O interfaces P0-P3 and G0-G3. All of these interfaces can be configured as PCIe link, some alternatively as {{abbr|xGMI}} link or S-Link, and some lanes as SATA, SATA Express, or XGBE link.
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| − | | |
| − | S-Link is a cache coherent link to {{abbr|CCIX}} memory expanders introduced on Type-1 processors. As AMD switched to [[wikipedia:Compute Express Link|CXL]], first available on {{\\|Socket SP5}}, support for S-Link and CCIX/PCIe ESM mode (using 25 GT/s PHYs on Type-1/2 IODs) was canceled.
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| − | | |
| − | [[wikipedia:SATA Express|SATA Express]] combines PCIe and SATA controllers on the same two lanes with a {{abbr|GPIO}} pin for a device to indicate its controller type. XGBE links support the [[wikipedia:10 Gigabit Ethernet#Backplane|10GBASE-KR]], [[wikipedia:Gigabit Ethernet#1000BASE-KX|1000BASE-KX]], and [[wikipedia:Media-independent interface#Serial gigabit media-independent interface|SGMII]] (10/100/1000 Mbit/s) backplane Ethernet protocols. The SATAe and XGBE functions are implemented on Type-0 processors but not Type-1/2, and support for these interfaces on Socket SP3 was withdrawn.
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| − | | |
| − | [[file:Socket SP3 2P routing.svg|DIMM order and 2P xGMI links]]
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| − | | |
| − | On dual socket (2P) systems the cache coherent xGMI links connect the Data Fabrics of each processor. Type-0 processors use four links, each attached to one die on the package, creating a NUMA system with three memory distances and one or two hops between any two dies. Type-1/2 processors can use three or four xGMI links depending on bandwidth requirements, all connected to the central I/O die. xGMI links use 16 lanes, unused links release 16 lanes per socket for I/O. The integrated {{abbr|SMU}} dynamically adjusts the link width (number of active lanes) for power saving.<!--Burd2018--> The {{abbr|WAFL}} link, one or two lanes, connect the Control Fabrics on each processor, i.e. the {{abbr|PSP}}, SMUs and other IPs, primarily for temperature monitoring, power and frequency control. Four socket systems are not supported although the available resources do not seem to rule this out.
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| − | | |
| − | Type-0 processors support DDR4-2666 memory and PCIe Gen 3 (8 GT/s) on their I/O links. Type-1/2 processors support DDR4-3200 memory and PCIe Gen 4 (16 GT/s), with xGMI links reaching 18 GT/s. Optimized motherboards are required to realize these data rates. Accordingly Type-1 processors can only run at restricted rates on Type-0 boards, after a BIOS update providing compatible firmware. Type-2 processors are not supported on first generation EPYC boards. Conversely EPYC 7001 "Naples" processors are incompatible with dual socket boards implementing only three xGMI links.
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| − | | |
| − | == Socket Description ==
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| − | Socket SP3, {{\\|Socket TR4|TR4}}, {{\\|Socket sTRX4|sTRX4}}, and {{\\|Socket sWRX8|sWRX8}} are mechanically identical. They have a 79.9 mm × 120.3 mm footprint and consist of the following components, from top to bottom:
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| − | | |
| − | * Force Frame
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| − | * Rail Frame
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| − | * Socket Housing
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| − | * Stiffener Frame
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| − | * Insulators
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| − | * Backplate
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| − | | |
| − | Removable components are:
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| − | | |
| − | * Heatsink
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| − | * Carrier Frame
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| − | * External Cap
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| − | * PnP Cover Cap
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| − | | |
| − | The force frame, rail frame, and stiffener frame constitute the Socket Actuation Mechanism. The heatsink, the CPU in a carrier frame, the SAM, housing, and backplate are separately orderable parts. The latter three are motherboard components for OEMs. Socket SP3 suppliers are [[wikipedia:Foxconn|Foxconn Interconnect Technology]] ([https://www.fit-foxconn.com website]) and Lotes Co. Ltd. ([https://www.lotes.cc/en website]).
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| − | | |
| − | {{abbr|LGA}} sockets use cantilever springs in the socket housing to make electrical contact with flat pads on the bottom of the CPU package. The SAM creates the Z-axis compression load between the CPU package and the housing soldered to the motherboard. Considerable force is required to deflect thousands of springs at once. According to AMD the SP3 SAM must exert a minimum force of 95 kg-f (932 N) to ensure proper mating of the package with the socket, a maximum of 125 kg-f (1226 N), so SP3 sockets are not actuated by a lever but three [[wikipedia:Torx|Torx]] screws linking their force frame and stiffener frame. The stiffener frame is attached to the backplate on the bottom side of the motherboard.
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| − | | |
| − | The '''force frame''' a.k.a. load plate is a largely flat piece stamped out of 2.0 mm thick stainless steel sheets. It has a window allowing the top of the CPU package lid to protrude for contact with the heatsink. When actuated it applies a load to the flanges on the sides of the lid. The force frame is attached to the stiffener frame by a hinge. It permits vertical motion when the socket is actuated, integrates a torsional spring to keep the frame open while the user inserts or removes the CPU, and a stop feature limiting the opening angle to some 105 degrees. The force frame is actuated by three [[wikipedia:Captive fastener|captive screws]] with a [[wikipedia:Torx|Torx]] T20 head and [[wikipedia:ISO metric screw thread|M3.5×0.6]] or larger thread. They mate with [[wikipedia:Swage nut|self-clinching PEM nuts]] on the stiffener frame.
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| − | | |
| − | These screws must be tightened in a particular order to avoid damage to the contact springs, the order is marked on the force frame. The lone screw opposite the hinge first, followed by the two screws next to it, with a maximum torque of 16.1 ± 1.2 kgf-cm (14.0 ± 1.0 lbf-in, 1.58 ± 0.1 N⋅m) according to AMD. {{amd|Ryzen Threadripper}} boxed processors come with a small preset torque limiting screwdriver for this purpose. Some sources recommend two passes to engage the threads, then tighten the screws. To remove the processor the screws should be opened in reverse order.
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| − | | |
| − | The '''rail frame''' together with the carrier frame constitute the package loading mechanism. Its main purpose is to minimize the risk of contact spring damage due to handling errors or accidents when loading the package into the housing. The rail frame is a stainless steel frame overmolded with black polycarbonate plastic and attached to the stiffener frame with a second hinge similar to the force frame. The steel frame forms a closed loop for stability and extends into a pair of finger lift tabs marked with blue color. The carrier frame slides into the rail frame along rails molded into both parts. They also have locking features which secure the carrier frame in the final position. When the rail frame is closed, latching features engage with undercut steps on the housing to ensure the package remains properly seated during actuation.
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| − | | |
| − | The '''carrier frame''' is made from colored polycarbonate material. EPYC 7001 series processors use blue, 7002 series green, 7003 series grey, and Threadripper processors (for {{\\|Socket TR4}}, {{\\|Socket sTRX4|sTRX4}}, and {{\\|Socket sWRX8|sWRX8}}) orange carriers. The carrier frame has a window for the package lid and a handle to pick up, insert, and remove the carrier without touching and contaminating the contact pads on the package. The handle bears the name of the supplier, commonly Lotes, and has a hole to provide access for one of the actuation screws. The opposite side of the frame is marked with a date and revision code. The carrier frame has six latches and is designed to snap onto the top side of the package substrate while the CPU package is sitting in the shipping tray. Keying features match two keying notches in the package to prevent it from being inserted 180 degrees rotated. Four alignment pegs on the carrier frame engage with alignment holes in the socket housing when the rail frame is closed.
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| − | | |
| − | The carrier frame is not supposed to be removed and not sold to consumers. Owners of a processor under warranty with a broken frame should contact the vendor or AMD customer service. Third parties may sell carrier frames salvaged from defective CPUs. If a replacement can or should be 3D-printed is unclear. It is evidently possible, with some care, to insert the package into the housing without the carrier.
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| − | | |
| − | The '''external cap''' is made from a transparent polycarbonate material. It has the same outer dimensions as the carrier frame, and the same rail and locking features to slide into the rail frame. The external cap ships with the SAM and protects the contact springs when no processor is installed in the socket. A label on its top side reminds users to remove the cap before inserting the processor. On the reverse side the external cap has a cavity fitting the cover cap, so the SAM with external cap can be installed over the housing with cover cap.
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| − | | |
| − | The '''cover cap''' is made from black [[wikipedia:Liquid-crystal polymer|liquid crystal polymer]] (LCP). It has the same alignment pegs as the carrier frame and latching features engaging with undercut steps on the housing, separate from those for the rail frame. The position of the pegs is asymmetric so the cap cannot be installed 180 degrees rotated. The cover cap ships with the socket housing and facilitates pick-and-place with a vacuum nozzle during board assembly. Its top protrusion has vent holes, bears the name of the socket and supplier, and serves as an alignment feature against the SAM with external cap.
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| − | | |
| − | The '''socket housing''' is a black LCP casing with two windows where [[wikipedia:Decoupling capacitor|decoupling capacitors]] can be placed on the top side of the motherboard. Its outline is asymmetric, preventing the SAM from being installed 180 degrees rotated. The walls have undercut steps on the outside for the rail frame and cover cap latches, cavities accomodating the carrier frame latches and keying features, finger access cut-outs in the middle of the long edges, and four alignment holes to receive the alignment pegs on the carrier frame. A chamfered corner marks the location of pin A1. The contact springs extend into a J-lead at the bottom of the housing with 0.6 mm diameter solder balls attached for [[wikipedia:Surface-mount technology|surface mounting]]. Standoffs limit the distance to the {{abbr|PCB}}.
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| − | | |
| − | The '''stiffener frame''' a.k.a. base plate is a flat, 1.7 mm thick stainless steel plate with a window fitting the socket housing, and seven [[wikipedia:Swage nut|self-clinching]], flush integrated nuts to fasten the force frame and a heatsink. The position of the four heatsink nuts (PEM nut standoffs) is asymmetric so the heatsink can only be installed in one orientation. They have a [[wikipedia:ISO metric screw thread|M3.5×0.6]] internal thread, and height 6.0 mm including the stiffener frame thickness or 6.18 mm from the top of the PCB. The top of the CPU package lid is 8.959 mm from the top of the PCB when the socket is actuated.
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| − | | |
| − | The SAM must be attached to a backplate on the bottom side of the motherboard or directly mounted to the chassis. This is facilitated by four M3.5×0.6 captive nuts on the stiffener frame with a Torx T20 head, a head diameter of 6.0 mm and maximum head height of 2.3 mm, to be tightened in a diagonal pattern with a maximum torque of 16.1 ± 1.2 kgf-cm (14.0 ± 1.0 lbf-in, 1.58 ± 0.1 N⋅m).
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| − | | |
| − | The '''backplate''' is a flat, 2.5 mm thick stainless steel plate with four self-clinching studs with a M3.5×0.6 external thread. Its dimensions are symmetric so it can be installed 180 degrees rotated, and like the housing it has a window for bottom side components. The studs protrude upwards through holes in the PCB and mate with the captive nuts on the stiffener frame. Backplates with stud heights between 4.0 and 5.6 mm are available to account for different PCB thicknesses.
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| − | | |
| − | Two sheets made from insulating material, 0.18 mm thick and about as large as the respective metal part separate the stiffener frame and backplate from the motherboard.
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| − | | |
| − | Socket SP3 processors require a '''heatsink'''. Heatsinks weighing up to 450 g can be mounted to the PEM nuts on the stiffener frame, heavier heatsinks require additional support such as direct chassis attachment. The allowable spring force exerted by the heatsink on the package lid is 75 ± 15 lb-f (334 ± 67 N). Thermal interface material should be applied between the lid and heatsink. The four captive spring screws on the heatsink should be tightened in a diagonal pattern with the same maximum torque of 16.1 ± 1.2 kgf-cm (14.0 ± 1.0 lbf-in, 1.58 ± 0.1 N⋅m) as the actuation screws.
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| − | | |
| − | == Feature Summary ==
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| − | * Lidded [[land grid array]] package, 75.40 mm × 58.50 mm
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| − | ** 4094 contacts in a 82 × 55 grid with 0.87 mm × 1.00 mm interstitial pitch
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| − | ** Organic substrate, [[flip chip]] die attachment
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| − | | |
| − | * 8 × 72 bit DDR4 SDRAM interface
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| − | ** Type-0 processors: Up to 1333 MHz, PC4-21333 (DDR4-2666), 170.67 GB/s total raw bandwidth
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| − | ** Type-1/2 processors: Up to 1600 MHz, PC4-25600 (DDR4-3200), 204.8 GB/s total raw bandwidth
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| − | ** Up to 2 DIMMs/channel, up to 16 DIMMs total
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| − | ** {{abbr|RDIMM}}, {{abbr|LRDIMM}}, {{abbr|3DS DIMM}}, {{abbr|NVDIMM-N}} types
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| − | ** ECC supported
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| − | ** Memory capacity 256 GiB/channel (Type-0) or 512 GiB/channel (Type-1/2)
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| | | | |
| − | * Eight multi-function I/O interfaces P0-P3, G0-G3
| + | === Supported Processors === |
| − | :{| class="wikitable" style="text-align:center"
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| − | |Lane||15||14||13||12||11||10||9||8||7||6||5||4||3||2||1||0
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| − | |-
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| − | | ||colspan="16"|xGMI
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| − | |-
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| − | | ||colspan="16"|S-Link
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| − | |-
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| − | |rowspan="5"|PCIe||colspan="16"|x16
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| − | |-
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| − | |colspan="8"|x8||colspan="8"|x8
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| − | |-
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| − | |colspan="4"|x4||colspan="4"|x4||colspan="4"|x4||colspan="4"|x4
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| − | |-
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| − | |colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2
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| − | |-
| |
| − | |x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1
| |
| − | |-
| |
| − | |SATAe||colspan="12"| ||colspan="2"|1||colspan="2"|0
| |
| − | |-
| |
| − | |SATA||colspan="8"| ||7||6||5||4||3||2||1||0
| |
| − | |-
| |
| − | |XGBE||colspan="8"| ||3||2||1||0||colspan="4"|
| |
| − | |-
| |
| − | |Type-0 PHYs||colspan="4"|PHY 4||colspan="4"|PHY 3||colspan="4"|PHY 2||colspan="2"|PHY 1||colspan="2"|PHY 0
| |
| − | |-
| |
| − | |Type-1/2 PHYs||colspan="4"|PHY 3||colspan="4"|PHY 2||colspan="4"|PHY 1||colspan="4"|PHY 0
| |
| − | |}
| |
| − | :* PCIe protocol supported on all interfaces
| |
| − | :** Type-0 processors: PCIe Gen 1, 2, 3 (8 GT/s)
| |
| − | :** Type-1/2 processors: PCIe Gen 1, 2, 3, 4 (16 GT/s)
| |
| − | :** 16 lanes, up to 8 ports per interface configurable x16, x8, x4, x2, x1 with power-of-two alignment (e.g. 1x4 + 4x1 + 1x8)
| |
| − | :** Max. 7 PCIe ports in each 8-lane subset (e.g. 0x8 + 8x1 is not possible)
| |
| − | :** Max. 7 PCIe ports per interface if any lane is configured as SATA port
| |
| − | :** Different PCIe generations supported on the ports in the same interface
| |
| − | :** Lane polarity inversion, per port lane reversal
| |
| − | :** Up to 128 PCIe lanes total on 1P systems
| |
| − | :** Up to 64 or 80 PCIe lanes total per socket on 2P systems
| |
| − | | |
| − | :* {{abbr|xGMI}} protocol supported on G0-G3, used on 2P systems only
| |
| − | :** Type-0 processors: Four x16 links per socket required
| |
| − | :** Type-1/2: Three or four links depending on bandwidth requirements
| |
| − | :** Four links: G0 (socket 0) ↔ G2 (socket 1), G1 ↔ G3, G2 ↔ G0, G3 ↔ G1
| |
| − | :** Three links: G0 ↔ G2, G1 ↔ G3, G2 ↔ G0
| |
| − | :** Max. raw data rate 18 GT/s (Type-1/2)
| |
| − | | |
| − | :* S-Link protocol on P0-P3
| |
| − | :** Not supported on Socket SP3
| |
| − | | |
| − | :* SATA Gen 1, 2, 3 (6 Gb/s) protocol supported on the lower 8 lanes of P0, P1, G2, G3
| |
| − | :** P0: SATA00-07, P1: SATA10-17, G2: SATA20-27, G3: SATA30-37
| |
| − | :** Up to 32 SATA ports total on 1P systems
| |
| − | :** Up to 16 SATA ports total per socket on 2P systems
| |
| − | | |
| − | :* XGBE protocols on lanes 4-7 of P0, P1, G2, G3
| |
| − | :** P0: XGBE00-03, P1: XGBE10-13, G2: XGBE20-23, G3: XGBE30-33
| |
| − | :** Not supported on Socket SP3
| |
| − | | |
| − | :* Five (Type-0 processors) or four (Type-1/2) {{abbr|PHY}} groups on each interface
| |
| − | :** Lanes sharing a PHY group must use the same protocol (PCIe, SATA)
| |
| − | :** On Type-0 platforms lanes 0-3 must use the same protocol for compatibility with Type-1 processors
| |
| − | | |
| − | * Supplementary I/O interface
| |
| − | ** PCIe Gen 1, 2 (5 GT/s), 2 lanes
| |
| − | ** {{abbr|WAFL}} interface on 2P systems
| |
| − | *** Option 1: WAFL[0] (socket 0) ↔ WAFL[1] (socket 1), WAFL[1] (s0) ↔ WAFL[0] (s1)
| |
| − | *** Option 2 (Type-1/2 only): WAFL[0] (s0) ↔ WAFL[1] (s1), WAFL[1] (s0) and WAFL[0] (s1) not used
| |
| − | ** Type-0 processors: Unused lanes remain unconnected
| |
| − | ** Type-1/2: Unused lanes are available for I/O, e.g. to attach a {{abbr|BMC}}
| |
| − | | |
| − | * 4 × USB 1.1, 2.0, 3.1 Gen 1 (5 Gb/s) ports
| |
| − | | |
| − | * Low speed interfaces (some sharing pins):
| |
| − | ** 8-bit {{abbr|eMMC}} v5.0 (400 MB/s)
| |
| − | ** 2 × 4-wire or 4 × 2-wire {{abbr|UART}} modeled after the [[wikipedia:16550 UART|16550]]
| |
| − | ** {{abbr|LPC}}, two clocks
| |
| − | ** 1/2/4-bit {{abbr|SPI/eSPI}} up to 100 MHz (SPI) and 66 MHz (eSPI)
| |
| − | ** 6 × {{abbr|I<sup>2</sup>C}}
| |
| − | ** 2 × {{abbr|SMBus}}
| |
| − | ** 4 × {{abbr|SGPIO}}
| |
| − | ** 2 × SATA {{abbr|DevSlp}}
| |
| − | ** 78 × {{abbr|GPIO}}
| |
| − | ** Sideband Interface a.k.a. {{abbr|APML}} ({{abbr|SB-RMI}}, {{abbr|SB-TSI}})
| |
| − | ** 2 × Serial VID Interface (SVI2)
| |
| − | ** {{abbr|JTAG}}
| |
| − | | |
| − | == Processors using Socket SP3 ==
| |
| | * {{#ask: [[Category:microprocessor models by amd]] | | * {{#ask: [[Category:microprocessor models by amd]] |
| | [[socket::Socket SP3]] | | [[socket::Socket SP3]] |
| Line 279: |
Line 47: |
| | |headers=show | | |headers=show |
| | |limit=0 | | |limit=0 |
| − | |searchlabel=Show processors for Socket SP3 | + | |searchlabel=Show Socket SP3-Supported Processors |
| | |class=sortable wikitable smwtable | | |class=sortable wikitable smwtable |
| | }} | | }} |
| − |
| |
| − | == Photos ==
| |
| − | <gallery widths=500px heights=400px>
| |
| − | File:amd naples (front).png|FCLGA-4094, package front
| |
| − | File:amd naples (back).png|FCLGA-4094, package back
| |
| − | File:Amd_socket_sp3_IMGP3469_smial_wp.jpg|Socket SP3, open
| |
| − | </gallery>
| |
| − |
| |
| − | == Package Diagrams ==
| |
| − | <!-- :[[File:sp3-details.png|1000px]] --><!--AMD-55423-3.0 (public version) Fig 1-->
| |
| − | [[File:LGA-4094 diag.svg]] <!--based on AMD-55260-1.16-->
| |
| − |
| |
| − | SP3 package. All dimensions in millimeters.
| |
| − |
| |
| − | {| style="text-align: center;"
| |
| − | |[[file:LGA-4094 SP3 Naples diag.svg]]<br/>"Naples" package
| |
| − | |
| |
| − | |[[file:LGA-4094 SP3 Rome diag.svg]]<br/>"Rome" package
| |
| − | |}
| |
| − |
| |
| − | [[File:LGA-4094 carrier diag.svg]]
| |
| − |
| |
| − | SP3 carrier frame (AMD ref. design, not Lotes). All dimensions in millimeters.
| |
| − |
| |
| − | == Socket Diagrams ==
| |
| − | [[File:Socket SP3 housing diag.svg]]
| |
| − |
| |
| − | Socket SP3 housing (AMD). The 4094 contact springs are not shown. All dimensions in millimeters.<br/> [[:File:Socket SP3 FIT housing diag.svg|Foxconn version]].
| |
| − |
| |
| − | [[File:Socket SP3 PCB layout.svg]]
| |
| − |
| |
| − | Socket SP3 PCB layout. NPTH = Non-Plated Through Hole. All dimensions in millimeters.
| |
| − |
| |
| − | == Pin Map ==
| |
| − | [[File:Socket SP3 pinmap.svg|800px]]
| |
| − |
| |
| − | Socket SP3 pinout, top view. This is a preview, click for a larger image and other views.
| |
| − |
| |
| − | <!--
| |
| − | AGPIO3/WOL0,CY24,MB_ADD[5],AY41,ME_DATA[8],CT2,MH_DATA[43],N6,VDDCR_CPU,F23,VDDIO_MEM_S3_EFGH,AG9,VSS,AA7,VSS,BY4
| |
| − | AGPIO4/WOL1,E17,MB_ADD[6],AY44,ME_DATA[9],CR1,MH_DATA[44],V5,VDDCR_CPU,F26,VDDIO_MEM_S3_EFGH,AH1,VSS,AA9,VSS,BY6
| |
| − | AGPIO5/DEVSLP0/WOL2,DB24,MB_ADD[7],AY43,ME_DATA[10],CM2,MH_DATA[45],V7,VDDCR_CPU,F29,VDDIO_MEM_S3_EFGH,AH4,VSS,AA11,VSS,BY8
| |
| − | AGPIO6/DEVSLP1/WOL3,DA24,MB_ADD[8],AY40,ME_DATA[11],CL1,MH_DATA[46],P5,VDDCR_CPU,F32,VDDIO_MEM_S3_EFGH,AH6,VSS,AA14,VSS,BY11
| |
| − | AGPIO9_0/SGPIO0_DATAOUT/MDIO1_SCL,DB29,MB_ADD[9],AW39,ME_DATA[12],CT3,MH_DATA[47],P7,VDDCR_CPU,F35,VDDIO_MEM_S3_EFGH,AH8,VSS,AA17,VSS,BY13
| |
| − | AGPIO23_0/SGPIO0_LOAD/MDIO1_SDA,CY27,MB_ADD[10],BE44,ME_DATA[13],CR3,MH_DATA[48],L5,VDDCR_CPU,F38,VDDIO_MEM_S3_EFGH,AH11,VSS,AA19,VSS,BY16
| |
| − | AGPIO40_0/SGPIO0_DATAIN/MDIO0_SDA,DA27,MB_ADD[11],AW40,ME_DATA[14],CM3,MH_DATA[49],L6,VDDCR_CPU,F40,VDDIO_MEM_S3_EFGH,AJ2,VSS,AA21,VSS,BY18
| |
| − | ALERT_L,CY39,MB_ADD[12],AV41,ME_DATA[15],CL3,MH_DATA[50],G5,VDDCR_CPU,F43,VDDIO_MEM_S3_EFGH,AJ4,VSS,AA23,VSS,BY20
| |
| − | BP[0],E40,MB_ADD[13],BG42,ME_DATA[16],CK2,MH_DATA[51],G6,VDDCR_CPU,F45,VDDIO_MEM_S3_EFGH,AJ7,VSS,AA25,VSS,BY24
| |
| − | BP[1],E41,MB_ADD_17,BH40,ME_DATA[17],CJ1,MH_DATA[52],M5,VDDCR_CPU,H11,VDDIO_MEM_S3_EFGH,AJ9,VSS,AA27,VSS,BY26
| |
| − | BP[2],D21,MB_ALERT_L,AV39,ME_DATA[18],CF2,MH_DATA[53],M7,VDDCR_CPU,H15,VDDIO_MEM_S3_EFGH,AK4,VSS,AA29,VSS,BY28
| |
| − | BP[3],C20,MB_BANK[0],BF41,ME_DATA[19],CE1,MH_DATA[54],H5,VDDCR_CPU,H18,VDDIO_MEM_S3_EFGH,AK6,VSS,AA31,VSS,BY30
| |
| − | BP[4],C22,MB_BANK[1],BE39,ME_DATA[20],CK3,MH_DATA[55],H7,VDDCR_CPU,H21,VDDIO_MEM_S3_EFGH,AK8,VSS,AA33,VSS,BY32
| |
| − | BP[5],C23,MB_BG[0],AU40,ME_DATA[21],CJ3,MH_DATA[56],E5,VDDCR_CPU,H24,VDDIO_MEM_S3_EFGH,AK11,VSS,AA35,VSS,BY34
| |
| − | CORETYPE,C29,MB_BG[1],AU39,ME_DATA[22],CF3,MH_DATA[57],E6,VDDCR_CPU,H27,VDDIO_MEM_S3_EFGH,AL2,VSS,AA37,VSS,BY36
| |
| − | CPU_PRESENT_L,B24,MB_CAS_L_ADD[15],BF43,ME_DATA[23],CE3,MH_DATA[58],B7,VDDCR_CPU,H30,VDDIO_MEM_S3_EFGH,AL4,VSS,AA38,VSS,BY39
| |
| − | DBREQ_L,B25,MB_CHECK[0],AP43,ME_DATA[24],CD2,MH_DATA[59],A7,VDDCR_CPU,H33,VDDIO_MEM_S3_EFGH,AL7,VSS,AA40,VSS,BY42
| |
| − | EGPIO9_1/SGPIO1_DATAOUT/MDIO3_SCL,D25,MB_CHECK[1],AP44,ME_DATA[25],CC1,MH_DATA[60],F5,VDDCR_CPU,H36,VDDIO_MEM_S3_EFGH,AL9,VSS,AA43,VSS,BY45
| |
| − | EGPIO9_2/SGPIO2_DATAOUT/MDIO5_SCL,D28,MB_CHECK[2],AV43,ME_DATA[26],BY2,MH_DATA[61],F7,VDDCR_CPU,H39,VDDIO_MEM_S3_EFGH,AM1,VSS,AA45,VSS,BY47
| |
| − | EGPIO9_3/SGPIO3_DATAOUT/MDIO7_SCL,CY41,MB_CHECK[3],AV44,ME_DATA[27],BW1,MH_DATA[62],B6,VDDCR_CPU,H42,VDDIO_MEM_S3_EFGH,AM4,VSS,AA48,VSS,BY49
| |
| − | EGPIO23_1/SGPIO1_LOAD/MDIO3_SDA,E25,MB_CHECK[4],AN42,ME_DATA[28],CD3,MH_DATA[63],A6,VDDCR_CPU,H45,VDDIO_MEM_S3_EFGH,AM6,VSS,AA50,VSS,BY52
| |
| − | EGPIO23_2/SGPIO2_LOAD/MDIO5_SDA,E28,MB_CHECK[5],AN44,ME_DATA[29],CC3,MH_DQS_H[0],CW5,VDDCR_CPU,K11,VDDIO_MEM_S3_EFGH,AM8,VSS,AA52,VSS,BY54
| |
| − | EGPIO23_3/SGPIO3_LOAD/MDIO7_SDA,CY42,MB_CHECK[6],AU42,ME_DATA[30],BY3,MH_DQS_H[1],CN5,VDDCR_CPU,K15,VDDIO_MEM_S3_EFGH,AM11,VSS,AA55,VSS,CA2
| |
| − | EGPIO40_1/SGPIO1_DATAIN/MDIO2_SDA,D24,MB_CHECK[7],AU44,ME_DATA[31],BW3,MH_DQS_H[2],CG5,VDDCR_CPU,K18,VDDIO_MEM_S3_EFGH,AN2,VSS,AB4,VSS,CA4
| |
| − | EGPIO40_2/SGPIO2_DATAIN/MDIO4_SDA,D27,MB_C[0],BJ39,ME_DATA[32],AD3,MH_DQS_H[3],CA5,VDDCR_CPU,K21,VDDIO_MEM_S3_EFGH,AN4,VSS,AB6,VSS,CA7
| |
| − | EGPIO40_3/SGPIO3_DATAIN/MDIO6_SDA,DB44,MB_C[1],BJ42,ME_DATA[33],AC3,MH_DQS_H[4],AA6,VDDCR_CPU,K24,VDDIO_MEM_S3_EFGH,AN7,VSS,AB8,VSS,CA9
| |
| − | EGPIO42,CV21,MB_C[2],BH43,ME_DATA[34],Y3,MH_DQS_H[5],R6,VDDCR_CPU,K27,VDDIO_MEM_S3_EFGH,AN9,VSS,AB11,VSS,CA11
| |
| − | EGPIO70/EMMC_CLK,CW25,MB_DATA[0],AB43,ME_DATA[35],W3,MH_DQS_H[6],J6,VDDCR_CPU,K30,VDDIO_MEM_S3_EFGH,AP4,VSS,AB13,VSS,CA14
| |
| − | ESPI_ALERT_L/LDRQ0_L/EGPIO108,CW24,MB_DATA[1],AB44,ME_DATA[36],AD2,MH_DQS_H[7],C6,VDDCR_CPU,K33,VDDIO_MEM_S3_EFGH,AP6,VSS,AB16,VSS,CA17
| |
| − | ESPI_RESET_L/KBRST_L/AGPIO129,CY29,MB_DATA[2],AF43,ME_DATA[37],AC1,MH_DQS_H[8],BR5,VDDCR_CPU,K36,VDDIO_MEM_S3_EFGH,AP8,VSS,AB18,VSS,CA19
| |
| − | FORCE_SELFREFRESH,A22,MB_DATA[3],AF44,ME_DATA[38],Y2,MH_DQS_H[9],CY7,VDDCR_CPU,K39,VDDIO_MEM_S3_EFGH,AP11,VSS,AB20,VSS,CA23
| |
| − | G0B_ZVSS,K29,MB_DATA[4],AA42,ME_DATA[39],W1,MH_DQS_H[10],CP7,VDDCR_CPU,K42,VDDIO_MEM_S3_EFGH,AP13,VSS,AB22,VSS,CA25
| |
| − | G0_RXN[0],V29,MB_DATA[5],AA44,ME_DATA[40],V3,MH_DQS_H[11],CH7,VDDCR_CPU,K45,VDDIO_MEM_S3_EFGH,AP16,VSS,AB26,VSS,CA27
| |
| − | G0_RXN[1],U29,MB_DATA[6],AE42,ME_DATA[41],U3,MH_DQS_H[12],CB7,VDDCR_CPU,M11,VDDIO_MEM_S3_EFGH,AR2,VSS,AB28,VSS,CA29
| |
| − | G0_RXN[2],W30,MB_DATA[7],AE44,ME_DATA[42],P3,MH_DQS_H[13],AB5,VDDCR_CPU,M15,VDDIO_MEM_S3_EFGH,AR4,VSS,AB30,VSS,CA31
| |
| − | G0_RXN[3],V32,MB_DATA[8],AB40,ME_DATA[43],N3,MH_DQS_H[14],T5,VDDCR_CPU,M18,VDDIO_MEM_S3_EFGH,AR7,VSS,AB32,VSS,CA33
| |
| − | G0_RXN[4],U32,MB_DATA[9],AB41,ME_DATA[44],V2,MH_DQS_H[15],K5,VDDCR_CPU,M21,VDDIO_MEM_S3_EFGH,AR9,VSS,AB36,VSS,CA34
| |
| − | G0_RXN[5],W33,MB_DATA[10],AF40,ME_DATA[45],U1,MH_DQS_H[16],D5,VDDCR_CPU,M24,VDDIO_MEM_S3_EFGH,AR11,VSS,AB38,VSS,CA37
| |
| − | G0_RXN[6],V35,MB_DATA[11],AF41,ME_DATA[46],P2,MH_DQS_H[17],BT7,VDDCR_CPU,M27,VDDIO_MEM_S3_EFGH,AR14,VSS,AB39,VSS,CA38
| |
| − | G0_RXN[7],U35,MB_DATA[12],AA39,ME_DATA[47],N1,MH_DQS_L[0],CY5,VDDCR_CPU,M30,VDDIO_MEM_S3_EFGH,AR17,VSS,AB42,VSS,CA40
| |
| − | G0_RXN[8],W36,MB_DATA[13],AA41,ME_DATA[48],M3,MH_DQS_L[1],CP5,VDDCR_CPU,M33,VDDIO_MEM_S3_EFGH,AR18,VSS,AB45,VSS,CA43
| |
| − | G0_RXN[9],V38,MB_DATA[14],AE39,ME_DATA[49],L3,MH_DQS_L[2],CH5,VDDCR_CPU,M36,VDDIO_MEM_S3_EFGH,AT1,VSS,AB47,VSS,CA45
| |
| − | G0_RXN[10],U38,MB_DATA[15],AE41,ME_DATA[50],H3,MH_DQS_L[3],CB5,VDDCR_CPU,M39,VDDIO_MEM_S3_EFGH,AT4,VSS,AB49,VSS,CA48
| |
| − | G0_RXN[11],W39,MB_DATA[16],AH43,ME_DATA[51],G3,MH_DQS_L[4],AB7,VDDCR_CPU,M42,VDDIO_MEM_S3_EFGH,AT6,VSS,AB52,VSS,CA50
| |
| − | G0_RXN[12],V41,MB_DATA[17],AH44,ME_DATA[52],M2,MH_DQS_L[5],T7,VDDCR_CPU,M45,VDDIO_MEM_S3_EFGH,AT8,VSS,AB54,VSS,CA52
| |
| − | G0_RXN[13],U41,MB_DATA[18],AM43,ME_DATA[53],L1,MH_DQS_L[6],K7,VDDCR_CPU,P11,VDDIO_MEM_S3_EFGH,AT11,VSS,AC2,VSS,CB1
| |
| − | G0_RXN[14],W42,MB_DATA[19],AM44,ME_DATA[54],H2,MH_DQS_L[7],D7,VDDCR_CPU,P15,VDDIO_MEM_S3_EFGH,AT13,VSS,AC4,VSS,CB4
| |
| − | G0_RXN[15],V44,MB_DATA[20],AG42,ME_DATA[55],G1,MH_DQS_L[8],BT5,VDDCR_CPU,P18,VDDIO_MEM_S3_EFGH,AT16,VSS,AC7,VSS,CB6
| |
| − | G0_RXP[0],W29,MB_DATA[21],AG44,ME_DATA[56],F3,MH_DQS_L[9],CW6,VDDCR_CPU,P21,VDDIO_MEM_S3_EFGH,AU2,VSS,AC9,VSS,CB8
| |
| − | G0_RXP[1],U30,MB_DATA[22],AL42,ME_DATA[57],E3,MH_DQS_L[10],CN6,VDDCR_CPU,P24,VDDIO_MEM_S3_EFGH,AU4,VSS,AC11,VSS,CB11
| |
| − | G0_RXP[2],V31,MB_DATA[23],AL44,ME_DATA[58],A3,MH_DQS_L[11],CG6,VDDCR_CPU,P27,VDDIO_MEM_S3_EFGH,AU7,VSS,AC14,VSS,CB13
| |
| − | G0_RXP[3],W32,MB_DATA[24],AH40,ME_DATA[59],A4,MH_DQS_L[12],CA6,VDDCR_CPU,P30,VDDIO_MEM_S3_EFGH,AU9,VSS,AC17,VSS,CB16
| |
| − | G0_RXP[4],U33,MB_DATA[25],AH41,ME_DATA[60],F2,MH_DQS_L[13],AA5,VDDCR_CPU,P33,VDDIO_MEM_S3_EFGH,AU11,VSS,AC19,VSS,CB18
| |
| − | G0_RXP[5],V34,MB_DATA[26],AM40,ME_DATA[61],E1,MH_DQS_L[14],R5,VDDCR_CPU,P36,VDDIO_MEM_S3_EFGH,AU14,VSS,AC21,VSS,CB20
| |
| − | G0_RXP[6],W35,MB_DATA[27],AM41,ME_DATA[62],B2,MH_DQS_L[15],J5,VDDCR_CPU,P39,VDDIO_MEM_S3_EFGH,AU17,VSS,AC25,VSS,CB22
| |
| − | G0_RXP[7],U36,MB_DATA[28],AG39,ME_DATA[63],B3,MH_DQS_L[16],C5,VDDCR_CPU,P42,VDDIO_MEM_S3_EFGH,AU18,VSS,AC27,VSS,CB24
| |
| − | G0_RXP[8],V37,MB_DATA[29],AG41,ME_DQS_H[0],CW1,MH_DQS_L[17],BR6,VDDCR_CPU,P45,VDDIO_MEM_S3_EFGH,AV4,VSS,AC29,VSS,CB26
| |
| − | G0_RXP[9],W38,MB_DATA[30],AL39,ME_DQS_H[1],CN1,MH_EVENT_L,AT5,VDDCR_CPU,T11,VDDIO_MEM_S3_EFGH,AV6,VSS,AC31,VSS,CB28
| |
| − | G0_RXP[10],U39,MB_DATA[31],AL41,ME_DQS_H[2],CG1,MH_PAROUT,AT7,VDDCR_CPU,T15,VDDIO_MEM_S3_EFGH,AV8,VSS,AC35,VSS,CB30
| |
| − | G0_RXP[11],V40,MB_DATA[32],BM41,ME_DQS_H[3],CA1,MH_RAS_L_ADD[16],AN5,VDDCR_CPU,T18,VDDIO_MEM_S3_EFGH,AV11,VSS,AC37,VSS,CB35
| |
| − | G0_RXP[12],W41,MB_DATA[33],BM40,ME_DQS_H[4],AA3,MH_RESET_L,BL6,VDDCR_CPU,T21,VDDIO_MEM_S3_EFGH,AV13,VSS,AC38,VSS,CB36
| |
| − | G0_RXP[13],U42,MB_DATA[34],BT41,ME_DQS_H[5],R3,MH_WE_L_ADD[14],AM5,VDDCR_CPU,T24,VDDIO_MEM_S3_EFGH,AV16,VSS,AC40,VSS,CB39
| |
| − | G0_RXP[14],V43,MB_DATA[35],BT40,ME_DQS_H[6],J3,MH_ZVSS,BA5,VDDCR_CPU,T27,VDDIO_MEM_S3_EFGH,AW2,VSS,AC43,VSS,CB42
| |
| − | G0_RXP[15],W44,MB_DATA[36],BL41,ME_DQS_H[7],C3,NV_SAVE_L,A38,VDDCR_CPU,T30,VDDIO_MEM_S3_EFGH,AW4,VSS,AC45,VSS,CB45
| |
| − | G0_TXN[0],L29,MB_DATA[37],BL39,ME_DQS_H[8],BR1,P0A_ZVSS,CT29,VDDCR_CPU,T33,VDDIO_MEM_S3_EFGH,AW7,VSS,AC48,VSS,CB47
| |
| − | G0_TXN[1],M31,MB_DATA[38],BR41,ME_DQS_H[9],CY3,P0_RXN[0]/SATA00_RXN/SATAE00_RXN0,CG44,VDDCR_CPU,T36,VDDIO_MEM_S3_EFGH,AW9,VSS,AC50,VSS,CB49
| |
| − | G0_TXN[2],K32,MB_DATA[39],BR39,ME_DQS_H[10],CP3,P0_RXN[1]/SATA01_RXN/SATAE00_RXN1,CH43,VDDCR_CPU,T39,VDDIO_MEM_S3_EFGH,AW11,VSS,AC52,VSS,CB52
| |
| − | G0_TXN[3],L32,MB_DATA[40],BM44,ME_DQS_H[11],CH3,P0_RXN[2]/SATA02_RXN/SATAE01_RXN0,CJ42,VDDCR_CPU,T42,VDDIO_MEM_S3_EFGH,AW14,VSS,AC55,VSS,CB54
| |
| − | G0_TXN[4],M34,MB_DATA[41],BM43,ME_DQS_H[12],CB3,P0_RXN[3]/SATA03_RXN/SATAE01_RXN1,CG41,VDDCR_CPU,T45,VDDIO_MEM_S3_EFGH,AW17,VSS,AD1,VSS,CC2
| |
| − | G0_TXN[5],K35,MB_DATA[42],BT44,ME_DQS_H[13],AB2,P0_RXN[4]/SATA04_RXN/XGBE00_RXN,CH40,VDDCR_CPU,V11,VDDIO_MEM_S3_EFGH,AW18,VSS,AD4,VSS,CC4
| |
| − | G0_TXN[6],L35,MB_DATA[43],BT43,ME_DQS_H[14],T2,P0_RXN[5]/SATA05_RXN/XGBE01_RXN,CJ39,VDDCR_CPU,V15,VDDIO_MEM_S3_EFGH,AY1,VSS,AD6,VSS,CC7
| |
| − | G0_TXN[7],M37,MB_DATA[44],BL44,ME_DQS_H[15],K2,P0_RXN[6]/SATA06_RXN/XGBE02_RXN,CG38,VDDCR_CPU,V18,VDDIO_MEM_S3_EFGH,AY4,VSS,AD8,VSS,CC9
| |
| − | G0_TXN[8],K38,MB_DATA[45],BL42,ME_DQS_H[16],D2,P0_RXN[7]/SATA07_RXN/XGBE03_RXN,CH37,VDDCR_CPU,V21,VDDIO_MEM_S3_EFGH,AY6,VSS,AD11,VSS,CC12
| |
| − | G0_TXN[9],L38,MB_DATA[46],BR44,ME_DQS_H[17],BT3,P0_RXN[8],CJ36,VDDCR_CPU,V24,VDDIO_MEM_S3_EFGH,AY8,VSS,AD13,VSS,CC14
| |
| − | G0_TXN[10],M40,MB_DATA[47],BR42,ME_DQS_L[0],CY2,P0_RXN[9],CG35,VDDCR_CPU,V27,VDDIO_MEM_S3_EFGH,AY11,VSS,AD16,VSS,CC15
| |
| − | G0_TXN[11],K41,MB_DATA[48],BV41,ME_DQS_L[1],CP2,P0_RXN[10],CH34,VDDCR_CPU,V30,VDDIO_MEM_S3_EFGH,AY13,VSS,AD18,VSS,CC17
| |
| − | G0_TXN[12],L41,MB_DATA[49],BV40,ME_DQS_L[2],CH2,P0_RXN[11],CJ33,VDDCR_CPU,V33,VDDIO_MEM_S3_EFGH,AY16,VSS,AD20,VSS,CC19
| |
| − | G0_TXN[13],M43,MB_DATA[50],CB41,ME_DQS_L[3],CB2,P0_RXN[12],CG32,VDDCR_CPU,V36,VDDIO_MEM_S3_EFGH,BA2,VSS,AD22,VSS,CC21
| |
| − | G0_TXN[14],K44,MB_DATA[51],CB40,ME_DQS_L[4],AB3,P0_RXN[13],CH31,VDDCR_CPU,V39,VDDIO_MEM_S3_EFGH,BA4,VSS,AD36,VSS,CC23
| |
| − | G0_TXN[15],L44,MB_DATA[52],BU41,ME_DQS_L[5],T3,P0_RXN[14],CJ30,VDDCR_CPU,V42,VDDIO_MEM_S3_EFGH,BA7,VSS,AD38,VSS,CC25
| |
| − | G0_TXP[0],M29,MB_DATA[53],BU39,ME_DQS_L[6],K3,P0_RXN[15],CG29,VDDCR_CPU,V45,VDDIO_MEM_S3_EFGH,BA9,VSS,AD39,VSS,CC27
| |
| − | G0_TXP[1],L30,MB_DATA[54],CA41,ME_DQS_L[7],D3,P0_RXP[0]/SATA00_RXP/SATAE00_RXP0,CH44,VDDCR_CPU,Y21,VDDIO_MEM_S3_EFGH,BA11,VSS,AD42,VSS,CC29
| |
| − | G0_TXP[2],K31,MB_DATA[55],CA39,ME_DQS_L[8],BT2,P0_RXP[1]/SATA01_RXP/SATAE00_RXP1,CG42,VDDCR_CPU,Y23,VDDIO_MEM_S3_EFGH,BA14,VSS,AD45,VSS,CC31
| |
| − | G0_TXP[3],M32,MB_DATA[56],BV44,ME_DQS_L[9],CW3,P0_RXP[2]/SATA02_RXP/SATAE01_RXP0,CJ41,VDDCR_CPU,Y25,VDDIO_MEM_S3_EFGH,BA17,VSS,AD47,VSS,CC34
| |
| − | G0_TXP[4],L33,MB_DATA[57],BV43,ME_DQS_L[10],CN3,P0_RXP[3]/SATA03_RXP/SATAE01_RXP1,CH41,VDDCR_CPU,Y27,VDDIO_MEM_S3_EFGH,BA18,VSS,AD49,VSS,CC35
| |
| − | G0_TXP[5],K34,MB_DATA[58],CB44,ME_DQS_L[11],CG3,P0_RXP[4]/SATA04_RXP/XGBE00_RXP,CG39,VDDCR_CPU,Y29,VDDIO_MEM_S3_EFGH,BB4,VSS,AD52,VSS,CC36
| |
| − | G0_TXP[6],M35,MB_DATA[59],CB43,ME_DQS_L[12],CA3,P0_RXP[5]/SATA05_RXP/XGBE01_RXP,CJ38,VDDCR_CPU,Y31,VDDIO_MEM_S3_EFGH,BB6,VSS,AD54,VSS,CC37
| |
| − | G0_TXP[7],L36,MB_DATA[60],BU44,ME_DQS_L[13],AA1,P0_RXP[6]/SATA06_RXP/XGBE02_RXP,CH38,VDDCR_CPU,Y33,VDDIO_MEM_S3_EFGH,BB8,VSS,AE1,VSS,CC38
| |
| − | G0_TXP[8],K37,MB_DATA[61],BU42,ME_DQS_L[14],R1,P0_RXP[7]/SATA07_RXP/XGBE03_RXP,CG36,VDDCR_CPU,Y35,VDDIO_MEM_S3_EFGH,BB11,VSS,AE2,VSS,CC39
| |
| − | G0_TXP[9],M38,MB_DATA[62],CA44,ME_DQS_L[15],J1,P0_RXP[8],CJ35,VDDCR_CPU,Y37,VDDIO_MEM_S3_EFGH,BB13,VSS,AE3,VSS,CC40
| |
| − | G0_TXP[10],L39,MB_DATA[63],CA42,ME_DQS_L[16],C1,P0_RXP[9],CH35,VDDCR_CPU,AA20,VDDIO_MEM_S3_EFGH,BB16,VSS,AE4,VSS,CC41
| |
| − | G0_TXP[11],K40,MB_DQS_H[0],AD44,ME_DQS_L[17],BR3,P0_RXP[10],CG33,VDDCR_CPU,AA22,VDDIO_MEM_S3_EFGH,BC2,VSS,AE5,VSS,CC42
| |
| − | G0_TXP[12],M41,MB_DQS_H[1],AD41,ME_EVENT_L,AU3,P0_RXP[11],CJ32,VDDCR_CPU,AA24,VDDIO_MEM_S3_EFGH,BC4,VSS,AE6,VSS,CC43
| |
| − | G0_TXP[13],L42,MB_DQS_H[2],AK44,ME_PAROUT,AT3,P0_RXP[12],CH32,VDDCR_CPU,AA26,VDDIO_MEM_S3_EFGH,BC7,VSS,AE7,VSS,CC44
| |
| − | G0_TXP[14],K43,MB_DQS_H[3],AK41,ME_RAS_L_ADD[16],AN1,P0_RXP[13],CG30,VDDCR_CPU,AA28,VDDIO_MEM_S3_EFGH,BC9,VSS,AE8,VSS,CC45
| |
| − | G0_TXP[15],M44,MB_DQS_H[4],BP40,ME_RESET_L,BL3,P0_RXP[14],CJ29,VDDCR_CPU,AA30,VDDIO_MEM_S3_EFGH,BC11,VSS,AE9,VSS,CC48
| |
| − | G1B_ZVSS,P29,MB_DQS_H[5],BP43,ME_WE_L_ADD[14],AN3,P0_RXP[15],CH29,VDDCR_CPU,AA32,VDDIO_MEM_S3_EFGH,BC14,VSS,AE10,VSS,CC50
| |
| − | G1_RXN[0],T29,MB_DQS_H[6],BY40,ME_ZVSS,BA3,P0_TXN[0]/SATA00_TXN/SATAE00_TXN0,CP44,VDDCR_CPU,AA34,VDDIO_MEM_S3_EFGH,BC17,VSS,AE11,VSS,CC52
| |
| − | G1_RXN[1],R30,MB_DQS_H[7],BY43,MF0_CKE[0],BH16,P0_TXN[1]/SATA01_TXN/SATAE00_TXN1,CT43,VDDCR_CPU,AA36,VDDIO_MEM_S3_EFGH,BC18,VSS,AE14,VSS,CC55
| |
| − | G1_RXN[2],P31,MB_DQS_H[8],AT44,MF0_CKE[1],BJ15,P0_TXN[2]/SATA02_TXN/SATAE01_TXN0,CR42,VDDCR_CPU,AB21,VDDIO_MEM_S3_EFGH,BD1,VSS,AE17,VSS,CD1
| |
| − | G1_RXN[3],T32,MB_DQS_H[9],AC42,MF0_CLK_H[0],AY12,P0_TXN[3]/SATA03_TXN/SATAE01_TXN1,CP41,VDDCR_CPU,AB23,VDDIO_MEM_S3_EFGH,BD4,VSS,AE19,VSS,CD4
| |
| − | G1_RXN[4],R33,MB_DQS_H[10],AC39,MF0_CLK_H[1],AY14,P0_TXN[4]/SATA04_TXN/XGBE00_TXN,CT40,VDDCR_CPU,AB25,VDDIO_MEM_S3_EFGH,BD6,VSS,AE21,VSS,CD6
| |
| − | G1_RXN[5],P34,MB_DQS_H[11],AJ42,MF0_CLK_L[0],AW12,P0_TXN[5]/SATA05_TXN/XGBE01_TXN,CR39,VDDCR_CPU,AB27,VDDIO_MEM_S3_EFGH,BD8,VSS,AE35,VSS,CD8
| |
| − | G1_RXN[6],T35,MB_DQS_H[12],AJ39,MF0_CLK_L[1],AW13,P0_TXN[6]/SATA06_TXN/XGBE02_TXN,CP38,VDDCR_CPU,AB29,VDDIO_MEM_S3_EFGH,BD11,VSS,AE37,VSS,CD11
| |
| − | G1_RXN[7],R36,MB_DQS_H[13],BN41,MF0_CS_L[0],AU12,P0_TXN[7]/SATA07_TXN/XGBE03_TXN,CT37,VDDCR_CPU,AB31,VDDIO_MEM_S3_EFGH,BD15,VSS,AE38,VSS,CD12
| |
| − | G1_RXN[8],P37,MB_DQS_H[14],BN44,MF0_CS_L[1],AR12,P0_TXN[8],CR36,VDDCR_CPU,AB33,VDDIO_MEM_S3_EFGH,BE2,VSS,AE40,VSS,CD15
| |
| − | G1_RXN[9],T38,MB_DQS_H[15],BW41,MF0_ODT[0],AT12,P0_TXN[9],CP35,VDDCR_CPU,AB35,VDDIO_MEM_S3_EFGH,BE4,VSS,AE43,VSS,CD18
| |
| − | G1_RXN[10],R39,MB_DQS_H[16],BW44,MF0_ODT[1],AP12,P0_TXN[10],CT34,VDDCR_CPU,AB37,VDDIO_MEM_S3_EFGH,BE7,VSS,AE45,VSS,CD21
| |
| − | G1_RXN[11],P40,MB_DQS_H[17],AR42,MF1_CKE[0],BG17,P0_TXN[11],CR33,VDDCR_CPU,AC20,VDDIO_MEM_S3_EFGH,BE9,VSS,AE48,VSS,CD24
| |
| − | G1_RXN[12],T41,MB_DQS_L[0],AC44,MF1_CKE[1],BH17,P0_TXN[12],CP32,VDDCR_CPU,AC22,VDDIO_MEM_S3_EFGH,BE16,VSS,AE50,VSS,CD27
| |
| − | G1_RXN[13],R42,MB_DQS_L[1],AC41,MF1_CLK_H[0],BA15,P0_TXN[13],CT31,VDDCR_CPU,AC24,VDDIO_MEM_S3_EFGH,BE18,VSS,AE52,VSS,CD30
| |
| − | G1_RXN[14],P43,MB_DQS_L[2],AJ44,MF1_CLK_H[1],BA16,P0_TXN[14],CR30,VDDCR_CPU,AC26,VDDIO_MEM_S3_EFGH,BF4,VSS,AF13,VSS,CD33
| |
| − | G1_RXN[15],T44,MB_DQS_L[3],AJ41,MF1_CLK_L[0],AY15,P0_TXN[15],CP29,VDDCR_CPU,AC28,VDDIO_MEM_S3_EFGH,BF6,VSS,AF16,VSS,CD36
| |
| − | G1_RXP[0],R29,MB_DQS_L[4],BN39,MF1_CLK_L[1],AY17,P0_TXP[0]/SATA00_TXP/SATAE00_TXP0,CR44,VDDCR_CPU,AC30,VDDIO_MEM_S3_EFGH,BF8,VSS,AF18,VSS,CD39
| |
| − | G1_RXP[1],T31,MB_DQS_L[5],BN42,MF1_CS_L[0],AU16,P0_TXP[1]/SATA01_TXP/SATAE00_TXP1,CT44,VDDCR_CPU,AC32,VDDIO_MEM_S3_EFGH,BF11,VSS,AF20,VSS,CD42
| |
| − | G1_RXP[2],P32,MB_DQS_L[6],BW39,MF1_CS_L[1],AR15,P0_TXP[2]/SATA02_TXP/SATAE01_TXP0,CP43,VDDCR_CPU,AC34,VDDIO_MEM_S3_EFGH,BF15,VSS,AF22,VSS,CD45
| |
| − | G1_RXP[3],R32,MB_DQS_L[7],BW42,MF1_ODT[0],AT17,P0_TXP[3]/SATA03_TXP/SATAE01_TXP1,CR41,VDDCR_CPU,AC36,VDDIO_MEM_S3_EFGH,BG2,VSS,AF36,VSS,CD47
| |
| − | G1_RXP[4],T34,MB_DQS_L[8],AR44,MF1_ODT[1],AP15,P0_TXP[4]/SATA04_TXP/XGBE00_TXP,CT41,VDDCR_CPU,AD21,VDDIO_MEM_S3_EFGH,BG4,VSS,AF38,VSS,CD49
| |
| − | G1_RXP[5],P35,MB_DQS_L[9],AD43,MF_ACT_L,BG15,P0_TXP[5]/SATA05_TXP/XGBE01_TXP,CP40,VDDCR_CPU,AD35,VDDIO_MEM_S3_EFGH,BG7,VSS,AF39,VSS,CD52
| |
| − | G1_RXP[6],R35,MB_DQS_L[10],AD40,MF_ADD[0],AV15,P0_TXP[6]/SATA06_TXP/XGBE02_TXP,CR38,VDDCR_CPU,AD37,VDDIO_MEM_S3_EFGH,BG9,VSS,AF42,VSS,CD54
| |
| − | G1_RXP[7],T37,MB_DQS_L[11],AK43,MF_ADD[1],BB12,P0_TXP[7]/SATA07_TXP/XGBE03_TXP,CT38,VDDCR_CPU,AE20,VDDIO_MEM_S3_EFGH,BG16,VSS,AF45,VSS,CE2
| |
| − | G1_RXP[8],P38,MB_DQS_L[12],AK40,MF_ADD[2],BB15,P0_TXP[8],CP37,VDDCR_CPU,AE34,VDDIO_MEM_S3_EFGH,BG18,VSS,AF47,VSS,CE4
| |
| − | G1_RXP[9],R38,MB_DQS_L[13],BP41,MF_ADD[3],BB17,P0_TXP[9],CR35,VDDCR_CPU,AE36,VDDIO_MEM_S3_EFGH,BH1,VSS,AF49,VSS,CE7
| |
| − | G1_RXP[10],T40,MB_DQS_L[14],BP44,MF_ADD[4],BB14,P0_TXP[10],CT35,VDDCR_CPU,AF19,VDDIO_MEM_S3_EFGH,BH4,VSS,AF52,VSS,CE9
| |
| − | G1_RXP[11],P41,MB_DQS_L[15],BY41,MF_ADD[5],BC15,P0_TXP[11],CP34,VDDCR_CPU,AF21,VDDIO_MEM_S3_EFGH,BH6,VSS,AF54,VSS,CE31
| |
| − | G1_RXP[12],R41,MB_DQS_L[16],BY44,MF_ADD[6],BC12,P0_TXP[12],CR32,VDDCR_CPU,AF35,VDDIO_MEM_S3_EFGH,BH8,VSS,AG11,VSS,CE34
| |
| − | G1_RXP[13],T43,MB_DQS_L[17],AT43,MF_ADD[7],BC13,P0_TXP[13],CT32,VDDCR_CPU,AF37,VDDIO_MEM_S3_EFGH,BH11,VSS,AG14,VSS,CE37
| |
| − | G1_RXP[14],P44,MB_EVENT_L,BD41,MF_ADD[8],BC16,P0_TXP[14],CP31,VDDCR_CPU,AG20,VDDIO_MEM_S3_EFGH,BH15,VSS,AG17,VSS,CE40
| |
| − | G1_RXP[15],R44,MB_PAROUT,BD40,MF_ADD[9],BD17,P0_TXP[15],CR29,VDDCR_CPU,AG34,VDDIO_MEM_S3_EFGH,BJ2,VSS,AG19,VSS,CE43
| |
| − | G1_TXN[0],J29,MB_RAS_L_ADD[16],BE42,MF_ADD[10],AV12,P1A_ZVSS,CF29,VDDCR_CPU,AG36,VDDIO_MEM_S3_EFGH,BJ4,VSS,AG21,VSS,CE45
| |
| − | G1_TXN[1],G30,MB_RESET_L,AP39,MF_ADD[11],BD16,P1_RXN[0]/SATA10_RXN/SATAE10_RXN0,CE44,VDDCR_CPU,AH19,VDDIO_MEM_S3_EFGH,BJ7,VSS,AG35,VSS,CE48
| |
| − | G1_TXN[2],H31,MB_WE_L_ADD[14],BG41,MF_ADD[12],BE15,P1_RXN[1]/SATA11_RXN/SATAE10_RXN1,CF44,VDDCR_CPU,AH21,VDDIO_MEM_S3_EFGH,BJ9,VSS,AG37,VSS,CE50
| |
| − | G1_TXN[3],J32,MB_ZVSS,BB44,MF_ADD[13],AT14,P1_RXN[2]/SATA12_RXN/SATAE11_RXN0,CD43,VDDCR_CPU,AH35,VDDIO_MEM_S3_EFGH,BJ16,VSS,AG38,VSS,CE52
| |
| − | G1_TXN[4],G33,MC0_CKE[0],AN47,MF_ADD_17,AR16,P1_RXN[3]/SATA13_RXN/SATAE11_RXN1,CE41,VDDCR_CPU,AH37,VDDIO_MEM_S3_EFGH,BK4,VSS,AG40,VSS,CE55
| |
| − | G1_TXN[5],H34,MC0_CKE[1],AM48,MF_ALERT_L,BE17,P1_RXN[4]/SATA14_RXN/XGBE10_RXN,CF41,VDDCR_CPU,AJ20,VDDIO_MEM_S3_EFGH,BK6,VSS,AG43,VSS,CF1
| |
| − | G1_TXN[6],J35,MC0_CLK_H[0],BC47,MF_BANK[0],AU15,P1_RXN[5]/SATA15_RXN/XGBE11_RXN,CD40,VDDCR_CPU,AJ34,VDDIO_MEM_S3_EFGH,BK8,VSS,AG45,VSS,CF4
| |
| − | G1_TXN[7],G36,MC0_CLK_H[1],BC46,MF_BANK[1],AV17,P1_RXN[6]/SATA16_RXN/XGBE12_RXN,CE38,VDDCR_CPU,AJ36,VDDIO_MEM_S3_EFGH,BK11,VSS,AG48,VSS,CF6
| |
| − | G1_TXN[8],H37,MC0_CLK_L[0],BD48,MF_BG[0],BF16,P1_RXN[7]/SATA17_RXN/XGBE13_RXN,CF38,VDDCR_CPU,AK19,VDDIO_MEM_S3_EFGH,BL2,VSS,AG50,VSS,CF8
| |
| − | G1_TXN[9],J38,MC0_CLK_L[1],BD46,MF_BG[1],BF17,P1_RXN[8],CD37,VDDCR_CPU,AK21,VDDIO_MEM_S3_EFGH,BL4,VSS,AG52,VSS,CF11
| |
| − | G1_TXN[10],G39,MC0_CS_L[0],BL46,MF_CAS_L_ADD[15],AU13,P1_RXN[9],CE35,VDDCR_CPU,AK35,VDDIO_MEM_S3_EFGH,BL7,VSS,AG55,VSS,CF12
| |
| − | G1_TXN[11],H40,MC0_CS_L[1],BP46,MF_CHECK[0],BJ13,P1_RXN[10],CF35,VDDCR_CPU,AK37,VDDIO_MEM_S3_EFGH,BL9,VSS,AH13,VSS,CF15
| |
| − | G1_TXN[12],J41,MC0_ODT[0],BN47,MF_CHECK[1],BJ12,P1_RXN[11],CD34,VDDCR_CPU,AL20,VDDIO_MEM_S3_EFGH_FB_H,BJ18,VSS,AH16,VSS,CF18
| |
| − | G1_TXN[13],G42,MC0_ODT[1],BT48,MF_CHECK[2],BE13,P1_RXN[12],CE32,VDDCR_CPU,AL34,VDDIO_MEM_S3_EFGH_FB_L,BK18,VSS,AH20,VSS,CF21
| |
| − | G1_TXN[14],H43,MC1_CKE[0],AP46,MF_CHECK[3],BE12,P1_RXN[13],CF32,VDDCR_CPU,AL36,VDD_18,Y17,VSS,AH22,VSS,CF24
| |
| − | G1_TXN[15],J44,MC1_CKE[1],AN46,MF_CHECK[4],BK14,P1_RXN[14],CD31,VDDCR_CPU,AM19,VDD_18,Y19,VSS,AH36,VSS,CF27
| |
| − | G1_TXP[0],H29,MC1_CLK_H[0],BE47,MF_CHECK[5],BK12,P1_RXN[15],CE29,VDDCR_CPU,AM21,VDD_18,AA18,VSS,AH38,VSS,CF30
| |
| − | G1_TXP[1],G29,MC1_CLK_H[1],BE46,MF_CHECK[6],BF14,P1_RXP[0]/SATA10_RXP/SATAE10_RXP0,CD44,VDDCR_CPU,AM35,VDD_18,AB19,VSS,AH39,VSS,CF33
| |
| − | G1_TXP[2],J30,MC1_CLK_L[0],BF48,MF_CHECK[7],BF12,P1_RXP[1]/SATA11_RXP/SATAE10_RXP1,CF43,VDDCR_CPU,AM37,VDD_18,AC18,VSS,AH42,VSS,CF36
| |
| − | G1_TXP[3],H32,MC1_CLK_L[1],BF46,MF_C[0],AP17,P1_RXP[2]/SATA12_RXP/SATAE11_RXP0,CE42,VDDCR_CPU,AN20,VDD_18,AD19,VSS,AH45,VSS,CF39
| |
| − | G1_TXP[4],G32,MC1_CS_L[0],BK46,MF_C[1],AP14,P1_RXP[3]/SATA13_RXP/SATAE11_RXP1,CD41,VDDCR_CPU,AN34,VDD_18,AE18,VSS,AH47,VSS,CF42
| |
| − | G1_TXP[5],J33,MC1_CS_L[1],BP48,MF_C[2],AR13,P1_RXP[4]/SATA14_RXP/XGBE10_RXP,CF40,VDDCR_CPU,AN36,VDD_18_S5,AG18,VSS,AH49,VSS,CF45
| |
| − | G1_TXP[6],H35,MC1_ODT[0],BM46,MF_DATA[0],CA13,P1_RXP[5]/SATA15_RXP/XGBE11_RXP,CE39,VDDCR_CPU,AP19,VDD_18_S5,AH18,VSS,AH52,VSS,CF47
| |
| − | G1_TXP[7],G35,MC1_ODT[1],BT46,MF_DATA[1],CA12,P1_RXP[6]/SATA16_RXP/XGBE12_RXP,CD38,VDDCR_CPU,AP21,VDD_18_S5_SENSE,CB33,VSS,AH54,VSS,CF49
| |
| − | G1_TXP[8],J36,MC_ACT_L,AP48,MF_DATA[2],BU13,P1_RXP[7]/SATA17_RXP/XGBE13_RXP,CF37,VDDCR_CPU,AP35,VDD_18_SENSE,Y13,VSS,AJ11,VSS,CF52
| |
| − | G1_TXP[9],H38,MC_ADD[0],BH48,MF_DATA[3],BU12,P1_RXP[8],CE36,VDDCR_CPU,AP37,VDD_33,CB37,VSS,AJ14,VSS,CF54
| |
| − | G1_TXP[10],G38,MC_ADD[1],BA46,MF_DATA[4],CB14,P1_RXP[9],CD35,VDDCR_CPU,AR20,VDD_33,CB38,VSS,AJ17,VSS,CG2
| |
| − | G1_TXP[11],J39,MC_ADD[2],BA47,MF_DATA[5],CB12,P1_RXP[10],CF34,VDDCR_CPU,AR34,VDD_33_S5,CA35,VSS,AJ18,VSS,CG4
| |
| − | G1_TXP[12],H41,MC_ADD[3],AY48,MF_DATA[6],BV14,P1_RXP[11],CE33,VDDCR_CPU,AR36,VDD_33_S5,CA36,VSS,AJ19,VSS,CG7
| |
| − | G1_TXP[13],G41,MC_ADD[4],AY46,MF_DATA[7],BV12,P1_RXP[12],CD32,VDDCR_CPU,AT19,VDD_33_S5_SENSE,CA32,VSS,AJ21,VSS,CG9
| |
| − | G1_TXP[14],J42,MC_ADD[5],AW47,MF_DATA[8],CA16,P1_RXP[13],CF31,VDDCR_CPU,AT21,VDD_33_SENSE,CC33,VSS,AJ35,VSS,CG31
| |
| − | G1_TXP[15],H44,MC_ADD[6],AW46,MF_DATA[9],CA15,P1_RXP[14],CE30,VDDCR_CPU,AT35,VSS,A5,VSS,AJ37,VSS,CG34
| |
| − | G2A_ZVSS,P28,MC_ADD[7],AV46,MF_DATA[10],BU16,P1_RXP[15],CD29,VDDCR_CPU,AT37,VSS,A8,VSS,AJ38,VSS,CG37
| |
| − | G2_RXN[0]/SATA20_RXN/SATAE20_RXN0,R12,MC_ADD[8],AV48,MF_DATA[11],BU15,P1_TXN[0]/SATA10_TXN/SATAE10_TXN0,CM44,VDDCR_CPU,AU20,VSS,A11,VSS,AJ40,VSS,CG40
| |
| − | G2_RXN[1]/SATA21_RXN/SATAE20_RXN1,P13,MC_ADD[9],AU46,MF_DATA[12],CB17,P1_TXN[1]/SATA11_TXN/SATAE10_TXN1,CL42,VDDCR_CPU,AU34,VSS,A12,VSS,AJ43,VSS,CG43
| |
| − | G2_RXN[2]/SATA22_RXN/SATAE21_RXN0,T14,MC_ADD[10],BJ47,MF_DATA[13],CB15,P1_TXN[2]/SATA12_TXN/SATAE11_TXN0,CN41,VDDCR_CPU,AU36,VSS,A15,VSS,AJ45,VSS,CG45
| |
| − | G2_RXN[3]/SATA23_RXN/SATAE21_RXN1,R15,MC_ADD[11],AU47,MF_DATA[14],BV17,P1_TXN[3]/SATA13_TXN/SATAE11_TXN1,CM41,VDDCR_CPU,AV19,VSS,A18,VSS,AJ48,VSS,CG48
| |
| − | G2_RXN[4]/SATA24_RXN/XGBE20_RXN,P16,MC_ADD[12],AT48,MF_DATA[15],BV15,P1_TXN[4]/SATA14_TXN/XGBE10_TXN,CL39,VDDCR_CPU,AV21,VSS,A21,VSS,AJ50,VSS,CG50
| |
| − | G2_RXN[5]/SATA25_RXN/XGBE21_RXN,T17,MC_ADD[13],BN46,MF_DATA[16],BR13,P1_TXN[5]/SATA15_TXN/XGBE11_TXN,CN38,VDDCR_CPU,AV35,VSS,A24,VSS,AJ52,VSS,CG52
| |
| − | G2_RXN[6]/SATA26_RXN/XGBE22_RXN,R18,MC_ADD_17,BR47,MF_DATA[17],BR12,P1_TXN[6]/SATA16_TXN/XGBE12_TXN,CM38,VDDCR_CPU,AV37,VSS,A27,VSS,AK13,VSS,CG55
| |
| − | G2_RXN[7]/SATA27_RXN/XGBE23_RXN,P19,MC_ALERT_L,AT46,MF_DATA[18],BL13,P1_TXN[7]/SATA17_TXN/XGBE13_TXN,CL36,VDDCR_CPU,AW20,VSS,A30,VSS,AK16,VSS,CH1
| |
| − | G2_RXN[8],T20,MC_BANK[0],BJ46,MF_DATA[19],BL12,P1_TXN[8],CN35,VDDCR_CPU,AW34,VSS,A33,VSS,AK18,VSS,CH4
| |
| − | G2_RXN[9],R21,MC_BANK[1],BH46,MF_DATA[20],BT14,P1_TXN[9],CM35,VDDCR_CPU,AW36,VSS,A36,VSS,AK20,VSS,CH6
| |
| − | G2_RXN[10],P22,MC_BG[0],AR47,MF_DATA[21],BT12,P1_TXN[10],CL33,VDDCR_CPU,AY19,VSS,A39,VSS,AK22,VSS,CH8
| |
| − | G2_RXN[11],T23,MC_BG[1],AR46,MF_DATA[22],BM14,P1_TXN[11],CN32,VDDCR_CPU,AY21,VSS,A42,VSS,AK36,VSS,CH11
| |
| − | G2_RXN[12],R24,MC_CAS_L_ADD[15],BM48,MF_DATA[23],BM12,P1_TXN[12],CM32,VDDCR_CPU,AY23,VSS,A45,VSS,AK38,VSS,CH12
| |
| − | G2_RXN[13],P25,MC_CHECK[0],AF46,MF_DATA[24],BR16,P1_TXN[13],CL30,VDDCR_CPU,AY25,VSS,A48,VSS,AK39,VSS,CH15
| |
| − | G2_RXN[14],T26,MC_CHECK[1],AF48,MF_DATA[25],BR15,P1_TXN[14],CN29,VDDCR_CPU,AY27,VSS,A51,VSS,AK42,VSS,CH18
| |
| − | G2_RXN[15],R27,MC_CHECK[2],AK46,MF_DATA[26],BL16,P1_TXN[15],CM29,VDDCR_CPU,AY29,VSS,B4,VSS,AK45,VSS,CH21
| |
| − | G2_RXP[0]/SATA20_RXP/SATAE20_RXP0,T13,MC_CHECK[3],AK48,MF_DATA[27],BL15,P1_TXP[0]/SATA10_TXP/SATAE10_TXP0,CL44,VDDCR_CPU,AY31,VSS,B5,VSS,AK47,VSS,CH24
| |
| − | G2_RXP[1]/SATA21_RXP/SATAE20_RXP1,P14,MC_CHECK[4],AE46,MF_DATA[28],BT17,P1_TXP[1]/SATA11_TXP/SATAE10_TXP1,CM43,VDDCR_CPU,AY33,VSS,B8,VSS,AK49,VSS,CH27
| |
| − | G2_RXP[2]/SATA22_RXP/SATAE21_RXP0,R14,MC_CHECK[5],AE47,MF_DATA[29],BT15,P1_TXP[2]/SATA12_TXP/SATAE11_TXP0,CN42,VDDCR_CPU,AY35,VSS,B47,VSS,AK52,VSS,CH30
| |
| − | G2_RXP[3]/SATA23_RXP/SATAE21_RXP1,T16,MC_CHECK[6],AJ46,MF_DATA[30],BM17,P1_TXP[3]/SATA13_TXP/SATAE11_TXP1,CL41,VDDCR_CPU,AY37,VSS,B49,VSS,AK54,VSS,CH33
| |
| − | G2_RXP[4]/SATA24_RXP/XGBE20_RXP,P17,MC_CHECK[7],AJ47,MF_DATA[31],BM15,P1_TXP[4]/SATA14_TXP/XGBE10_TXP,CM40,VDDCR_CPU,BA20,VSS,B52,VSS,AL11,VSS,CH36
| |
| − | G2_RXP[5]/SATA25_RXP/XGBE21_RXP,R17,MC_C[0],BU46,MF_DATA[32],AL15,P1_TXP[5]/SATA15_TXP/XGBE11_TXP,CN39,VDDCR_CPU,BA22,VSS,C2,VSS,AL14,VSS,CH39
| |
| − | G2_RXP[6]/SATA26_RXP/XGBE22_RXP,T19,MC_C[1],BU47,MF_DATA[33],AL16,P1_TXP[6]/SATA16_TXP/XGBE12_TXP,CL38,VDDCR_CPU,BA24,VSS,C4,VSS,AL17,VSS,CH42
| |
| − | G2_RXP[7]/SATA27_RXP/XGBE23_RXP,P20,MC_C[2],BR46,MF_DATA[34],AG15,P1_TXP[7]/SATA17_TXP/XGBE13_TXP,CM37,VDDCR_CPU,BA26,VSS,C7,VSS,AL18,VSS,CH45
| |
| − | G2_RXP[8],R20,MC_DATA[0],A47,MF_DATA[35],AG16,P1_TXP[8],CN36,VDDCR_CPU,BA28,VSS,C9,VSS,AL19,VSS,CH47
| |
| − | G2_RXP[9],T22,MC_DATA[1],B48,MF_DATA[36],AM15,P1_TXP[9],CL35,VDDCR_CPU,BA30,VSS,C11,VSS,AL21,VSS,CH49
| |
| − | G2_RXP[10],P23,MC_DATA[2],F46,MF_DATA[37],AM17,P1_TXP[10],CM34,VDDCR_CPU,BA32,VSS,C12,VSS,AL35,VSS,CH52
| |
| − | G2_RXP[11],R23,MC_DATA[3],F48,MF_DATA[38],AH15,P1_TXP[11],CN33,VDDCR_CPU,BA34,VSS,C15,VSS,AL37,VSS,CH54
| |
| − | G2_RXP[12],T25,MC_DATA[4],B46,MF_DATA[39],AH17,P1_TXP[12],CL32,VDDCR_CPU,BA36,VSS,C18,VSS,AL38,VSS,CJ2
| |
| − | G2_RXP[13],P26,MC_DATA[5],A46,MF_DATA[40],AL12,P1_TXP[13],CM31,VDDCR_CPU,BB19,VSS,C21,VSS,AL40,VSS,CJ4
| |
| − | G2_RXP[14],R26,MC_DATA[6],E46,MF_DATA[41],AL13,P1_TXP[14],CN30,VDDCR_CPU,BB21,VSS,C24,VSS,AL43,VSS,CJ7
| |
| − | G2_RXP[15],T28,MC_DATA[7],E47,MF_DATA[42],AG12,P1_TXP[15],CL29,VDDCR_CPU,BB23,VSS,C27,VSS,AL45,VSS,CJ9
| |
| − | G2_TXN[0]/SATA20_TXN/SATAE20_TXN0,H13,MC_DATA[8],H46,MF_DATA[43],AG13,P2B_ZVSS,CF28,VDDCR_CPU,BB25,VSS,C30,VSS,AL46,VSS,CJ31
| |
| − | G2_TXN[1]/SATA21_TXN/SATAE20_TXN1,J14,MC_DATA[9],H48,MF_DATA[44],AM12,P2_RXN[0],CD28,VDDCR_CPU,BB27,VSS,C33,VSS,AL47,VSS,CJ37
| |
| − | G2_TXN[2]/SATA22_TXN/SATAE21_TXN0,G15,MC_DATA[10],M46,MF_DATA[45],AM14,P2_RXN[1],CE26,VDDCR_CPU,BB29,VSS,C36,VSS,AL48,VSS,CJ40
| |
| − | G2_TXN[3]/SATA23_TXN/SATAE21_TXN1,H16,MC_DATA[11],M48,MF_DATA[46],AH12,P2_RXN[2],CF26,VDDCR_CPU,BB31,VSS,C39,VSS,AL49,VSS,CJ43
| |
| − | G2_TXN[4]/SATA24_TXN/XGBE20_TXN,J17,MC_DATA[12],G46,MF_DATA[47],AH14,P2_RXN[3],CD25,VDDCR_CPU,BB33,VSS,C42,VSS,AL50,VSS,CJ45
| |
| − | G2_TXN[5]/SATA25_TXN/XGBE21_TXN,G18,MC_DATA[13],G47,MF_DATA[48],AE15,P2_RXN[4],CE23,VDDCR_CPU,BB35,VSS,C45,VSS,AL51,VSS,CJ48
| |
| − | G2_TXN[6]/SATA26_TXN/XGBE22_TXN,H19,MC_DATA[14],L46,MF_DATA[49],AE16,P2_RXN[5],CF23,VDDCR_CPU,BB37,VSS,C48,VSS,AL52,VSS,CJ50
| |
| − | G2_TXN[7]/SATA27_TXN/XGBE23_TXN,J20,MC_DATA[15],L47,MF_DATA[50],AA15,P2_RXN[6],CD22,VDDCR_CPU,BC20,VSS,C50,VSS,AL53,VSS,CJ52
| |
| − | G2_TXN[8],G21,MC_DATA[16],P46,MF_DATA[51],AA16,P2_RXN[7],CE20,VDDCR_CPU,BC22,VSS,C52,VSS,AL54,VSS,CJ55
| |
| − | G2_TXN[9],H22,MC_DATA[17],P48,MF_DATA[52],AF15,P2_RXN[8],CF20,VDDCR_CPU,BC24,VSS,C55,VSS,AL55,VSS,CK1
| |
| − | G2_TXN[10],J23,MC_DATA[18],V46,MF_DATA[53],AF17,P2_RXN[9],CD19,VDDCR_CPU,BC26,VSS,D1,VSS,AM13,VSS,CK4
| |
| − | G2_TXN[11],G24,MC_DATA[19],V48,MF_DATA[54],AB15,P2_RXN[10],CE17,VDDCR_CPU,BC28,VSS,D4,VSS,AM16,VSS,CK6
| |
| − | G2_TXN[12],H25,MC_DATA[20],N46,MF_DATA[55],AB17,P2_RXN[11],CF17,VDDCR_CPU,BC30,VSS,D6,VSS,AM18,VSS,CK8
| |
| − | G2_TXN[13],J26,MC_DATA[21],N47,MF_DATA[56],AE12,P2_RXN[12],CD16,VDDCR_CPU,BC32,VSS,D8,VSS,AM20,VSS,CK11
| |
| − | G2_TXN[14],G27,MC_DATA[22],U46,MF_DATA[57],AE13,P2_RXN[13],CE14,VDDCR_CPU,BC34,VSS,D47,VSS,AM22,VSS,CK12
| |
| − | G2_TXN[15],H28,MC_DATA[23],U47,MF_DATA[58],AA12,P2_RXN[14],CF14,VDDCR_CPU,BC36,VSS,D49,VSS,AM36,VSS,CK13
| |
| − | G2_TXP[0]/SATA20_TXP/SATAE20_TXP0,J12,MC_DATA[24],Y46,MF_DATA[59],AA13,P2_RXN[15],CD13,VDDCR_CPU,BD19,VSS,D52,VSS,AM38,VSS,CK14
| |
| − | G2_TXP[1]/SATA21_TXP/SATAE20_TXP1,H14,MC_DATA[25],Y48,MF_DATA[60],AF12,P2_RXP[0],CE27,VDDCR_CPU,BD21,VSS,D54,VSS,AM39,VSS,CK15
| |
| − | G2_TXP[2]/SATA22_TXP/SATAE21_TXP0,G14,MC_DATA[26],AD46,MF_DATA[61],AF14,P2_RXP[1],CD26,VDDCR_CPU,BD35,VSS,E2,VSS,AM42,VSS,CK16
| |
| − | G2_TXP[3]/SATA23_TXP/SATAE21_TXP1,J15,MC_DATA[27],AD48,MF_DATA[62],AB12,P2_RXP[2],CF25,VDDCR_CPU,BD37,VSS,E4,VSS,AM45,VSS,CK17
| |
| − | G2_TXP[4]/SATA24_TXP/XGBE20_TXP,H17,MC_DATA[28],W46,MF_DATA[63],AB14,P2_RXP[3],CE24,VDDCR_CPU,BE20,VSS,E7,VSS,AN11,VSS,CK18
| |
| − | G2_TXP[5]/SATA25_TXP/XGBE21_TXP,G17,MC_DATA[29],W47,MF_DQS_H[0],BW12,P2_RXP[4],CD23,VDDCR_CPU,BE34,VSS,E9,VSS,AN12,VSS,CK19
| |
| − | G2_TXP[6]/SATA26_TXP/XGBE22_TXP,J18,MC_DATA[30],AC46,MF_DQS_H[1],BW15,P2_RXP[5],CF22,VDDCR_CPU,BE36,VSS,E11,VSS,AN13,VSS,CK20
| |
| − | G2_TXP[7]/SATA27_TXP/XGBE23_TXP,H20,MC_DATA[31],AC47,MF_DQS_H[2],BN12,P2_RXP[6],CE21,VDDCR_CPU,BF19,VSS,E12,VSS,AN14,VSS,CK21
| |
| − | G2_TXP[8],G20,MC_DATA[32],BY48,MF_DQS_H[3],BN15,P2_RXP[7],CD20,VDDCR_CPU,BF21,VSS,E15,VSS,AN15,VSS,CK22
| |
| − | G2_TXP[9],J21,MC_DATA[33],BY46,MF_DQS_H[4],AJ16,P2_RXP[8],CF19,VDDCR_CPU,BF35,VSS,E18,VSS,AN16,VSS,CK23
| |
| − | G2_TXP[10],H23,MC_DATA[34],CD48,MF_DQS_H[5],AJ13,P2_RXP[9],CE18,VDDCR_CPU,BF37,VSS,E21,VSS,AN17,VSS,CK24
| |
| − | G2_TXP[11],G23,MC_DATA[35],CD46,MF_DQS_H[6],AC16,P2_RXP[10],CD17,VDDCR_CPU,BG20,VSS,E24,VSS,AN18,VSS,CK25
| |
| − | G2_TXP[12],J24,MC_DATA[36],BW47,MF_DQS_H[7],AC13,P2_RXP[11],CF16,VDDCR_CPU,BG34,VSS,E27,VSS,AN19,VSS,CK26
| |
| − | G2_TXP[13],H26,MC_DATA[37],BW46,MF_DQS_H[8],BG12,P2_RXP[12],CE15,VDDCR_CPU,BG36,VSS,E30,VSS,AN21,VSS,CK27
| |
| − | G2_TXP[14],G26,MC_DATA[38],CC47,MF_DQS_H[9],BY14,P2_RXP[13],CD14,VDDCR_CPU,BH19,VSS,E33,VSS,AN35,VSS,CK28
| |
| − | G2_TXP[15],J27,MC_DATA[39],CC46,MF_DQS_H[10],BY17,P2_RXP[14],CF13,VDDCR_CPU,BH21,VSS,E36,VSS,AN37,VSS,CK29
| |
| − | G3A_ZVSS,K28,MC_DATA[40],CF48,MF_DQS_H[11],BP14,P2_RXP[15],CE12,VDDCR_CPU,BH35,VSS,E39,VSS,AN39,VSS,CK30
| |
| − | G3_RXN[0]/SATA30_RXN/SATAE30_RXN0,W12,MC_DATA[41],CF46,MF_DQS_H[12],BP17,P2_TXN[0],CL27,VDDCR_CPU,BH37,VSS,E42,VSS,AN40,VSS,CK31
| |
| − | G3_RXN[1]/SATA31_RXN/SATAE30_RXN1,V14,MC_DATA[42],CK48,MF_DQS_H[13],AK15,P2_TXN[1],CN26,VDDCR_CPU,BJ20,VSS,E45,VSS,AN41,VSS,CK32
| |
| − | G3_RXN[2]/SATA32_RXN/SATAE31_RXN0,U14,MC_DATA[43],CK46,MF_DQS_H[14],AK12,P2_TXN[2],CM26,VDDCR_CPU,BJ34,VSS,E48,VSS,AN43,VSS,CK33
| |
| − | G3_RXN[3]/SATA33_RXN/SATAE31_RXN1,W15,MC_DATA[44],CE47,MF_DQS_H[15],AD15,P2_TXN[3],CL24,VDDCR_CPU,BJ36,VSS,E50,VSS,AP18,VSS,CK35
| |
| − | G3_RXN[4]/SATA34_RXN/XGBE30_RXN,V17,MC_DATA[45],CE46,MF_DQS_H[16],AD12,P2_TXN[4],CN23,VDDCR_CPU,BK19,VSS,E52,VSS,AP20,VSS,CK36
| |
| − | G3_RXN[5]/SATA35_RXN/XGBE31_RXN,U17,MC_DATA[46],CJ47,MF_DQS_H[17],BH14,P2_TXN[5],CM23,VDDCR_CPU,BK21,VSS,E55,VSS,AP22,VSS,CK37
| |
| − | G3_RXN[6]/SATA36_RXN/XGBE32_RXN,W18,MC_DATA[47],CJ46,MF_DQS_L[0],BY12,P2_TXN[6],CL21,VDDCR_CPU,BK35,VSS,F1,VSS,AP36,VSS,CK38
| |
| − | G3_RXN[7]/SATA37_RXN/XGBE33_RXN,V20,MC_DATA[48],CM48,MF_DQS_L[1],BY15,P2_TXN[7],CN20,VDDCR_CPU,BK37,VSS,F4,VSS,AP42,VSS,CK39
| |
| − | G3_RXN[8],U20,MC_DATA[49],CM46,MF_DQS_L[2],BP12,P2_TXN[8],CM20,VDDCR_CPU,BL20,VSS,F6,VSS,AP45,VSS,CK40
| |
| − | G3_RXN[9],W21,MC_DATA[50],CT48,MF_DQS_L[3],BP15,P2_TXN[9],CL18,VDDCR_CPU,BL34,VSS,F8,VSS,AR19,VSS,CK41
| |
| − | G3_RXN[10],V23,MC_DATA[51],CT46,MF_DQS_L[4],AK17,P2_TXN[10],CN17,VDDCR_CPU,BL36,VSS,F13,VSS,AR21,VSS,CK42
| |
| − | G3_RXN[11],U23,MC_DATA[52],CL47,MF_DQS_L[5],AK14,P2_TXN[11],CM17,VDDCR_CPU,BM19,VSS,F15,VSS,AR35,VSS,CK43
| |
| − | G3_RXN[12],W24,MC_DATA[53],CL46,MF_DQS_L[6],AD17,P2_TXN[12],CL15,VDDCR_CPU,BM21,VSS,F16,VSS,AR37,VSS,CK44
| |
| − | G3_RXN[13],V26,MC_DATA[54],CR47,MF_DQS_L[7],AD14,P2_TXN[13],CN14,VDDCR_CPU,BM35,VSS,F18,VSS,AR38,VSS,CK45
| |
| − | G3_RXN[14],U26,MC_DATA[55],CR46,MF_DQS_L[8],BH12,P2_TXN[14],CM14,VDDCR_CPU,BM37,VSS,F19,VSS,AR43,VSS,CK47
| |
| − | G3_RXN[15],W27,MC_DATA[56],CV48,MF_DQS_L[9],BW13,P2_TXN[15],CL12,VDDCR_CPU,BN20,VSS,F21,VSS,AT18,VSS,CK49
| |
| − | G3_RXP[0]/SATA30_RXP/SATAE30_RXP0,V13,MC_DATA[57],CV46,MF_DQS_L[10],BW16,P2_TXP[0],CM28,VDDCR_CPU,BN34,VSS,F22,VSS,AT20,VSS,CK52
| |
| − | G3_RXP[1]/SATA31_RXP/SATAE30_RXP1,W14,MC_DATA[58],DA46,MF_DQS_L[11],BN13,P2_TXP[1],CN27,VDDCR_CPU,BN36,VSS,F24,VSS,AT22,VSS,CK54
| |
| − | G3_RXP[2]/SATA32_RXP/SATAE31_RXP0,U15,MC_DATA[59],DB46,MF_DQS_L[12],BN16,P2_TXP[2],CL26,VDDCR_CPU,BP19,VSS,F25,VSS,AT36,VSS,CL2
| |
| − | G3_RXP[3]/SATA33_RXP/SATAE31_RXP1,V16,MC_DATA[60],CU47,MF_DQS_L[13],AJ15,P2_TXP[3],CM25,VDDCR_CPU,BP21,VSS,F27,VSS,AT42,VSS,CL4
| |
| − | G3_RXP[4]/SATA34_RXP/XGBE30_RXP,W17,MC_DATA[61],CU46,MF_DQS_L[14],AJ12,P2_TXP[4],CN24,VDDCR_CPU,BP35,VSS,F28,VSS,AT45,VSS,CL7
| |
| − | G3_RXP[5]/SATA35_RXP/XGBE31_RXP,U18,MC_DATA[62],DA47,MF_DQS_L[15],AC15,P2_TXP[5],CL23,VDDCR_CPU,BP37,VSS,F30,VSS,AU19,VSS,CL9
| |
| − | G3_RXP[6]/SATA36_RXP/XGBE32_RXP,V19,MC_DATA[63],DB47,MF_DQS_L[16],AC12,P2_TXP[6],CM22,VDDCR_CPU,BR20,VSS,F31,VSS,AU21,VSS,CL31
| |
| − | G3_RXP[7]/SATA37_RXP/XGBE33_RXP,W20,MC_DQS_H[0],D48,MF_DQS_L[17],BG13,P2_TXP[7],CN21,VDDCR_CPU,BR34,VSS,F33,VSS,AU35,VSS,CL34
| |
| − | G3_RXP[8],U21,MC_DQS_H[1],K48,MF_EVENT_L,AW15,P2_TXP[8],CL20,VDDCR_CPU,BR36,VSS,F34,VSS,AU37,VSS,CL37
| |
| − | G3_RXP[9],V22,MC_DQS_H[2],T48,MF_PAROUT,AW16,P2_TXP[9],CM19,VDDCR_CPU,BT19,VSS,F36,VSS,AU38,VSS,CL40
| |
| − | G3_RXP[10],W23,MC_DQS_H[3],AB48,MF_RAS_L_ADD[16],AV14,P2_TXP[10],CN18,VDDCR_CPU,BT21,VSS,F37,VSS,AU43,VSS,CL43
| |
| − | G3_RXP[11],U24,MC_DQS_H[4],CB46,MF_RESET_L,BJ17,P2_TXP[11],CL17,VDDCR_CPU,BT35,VSS,F39,VSS,AV18,VSS,CL45
| |
| − | G3_RXP[12],V25,MC_DQS_H[5],CH46,MF_WE_L_ADD[14],AT15,P2_TXP[12],CM16,VDDCR_CPU,BT37,VSS,F47,VSS,AV20,VSS,CL48
| |
| − | G3_RXP[13],W26,MC_DQS_H[6],CP46,MF_ZVSS,BA12,P2_TXP[13],CN15,VDDCR_CPU,BU20,VSS,F49,VSS,AV22,VSS,CL50
| |
| − | G3_RXP[14],U27,MC_DQS_H[7],CY46,MG0_CKE[0],BK9,P2_TXP[14],CL14,VDDCR_CPU,BU34,VSS,F52,VSS,AV36,VSS,CL52
| |
| − | G3_RXP[15],V28,MC_DQS_H[8],AH48,MG0_CKE[1],BL8,P2_TXP[15],CM13,VDDCR_CPU,BU36,VSS,F54,VSS,AV42,VSS,CL55
| |
| − | G3_TXN[0]/SATA30_TXN/SATAE30_TXN0,M13,MC_DQS_H[9],C46,MG0_CLK_H[0],AY9,P3B_ZVSS,CT28,VDDCR_CPU,BV19,VSS,G2,VSS,AV45,VSS,CM1
| |
| − | G3_TXN[1]/SATA31_TXN/SATAE30_TXN1,K14,MC_DQS_H[10],J46,MG0_CLK_H[1],AY10,P3_RXN[0],CH28,VDDCR_CPU,BV21,VSS,G4,VSS,AW19,VSS,CM4
| |
| − | G3_TXN[2]/SATA32_TXN/SATAE31_TXN0,L14,MC_DQS_H[11],R46,MG0_CLK_L[0],AW8,P3_RXN[1],CJ27,VDDCR_CPU,BV35,VSS,G7,VSS,AW21,VSS,CM6
| |
| − | G3_TXN[3]/SATA33_TXN/SATAE31_TXN1,M16,MC_DQS_H[12],AA46,MG0_CLK_L[1],AW10,P3_RXN[2],CG26,VDDCR_CPU,BV37,VSS,G9,VSS,AW35,VSS,CM8
| |
| − | G3_TXN[4]/SATA34_TXN/XGBE30_TXN,K17,MC_DQS_H[13],CA47,MG0_CS_L[0],AM10,P3_RXN[3],CH25,VDDCR_CPU,BW20,VSS,G11,VSS,AW37,VSS,CM11
| |
| − | G3_TXN[5]/SATA35_TXN/XGBE31_TXN,L17,MC_DQS_H[14],CG47,MG0_CS_L[1],AJ10,P3_RXN[4],CJ24,VDDCR_CPU,BW34,VSS,G13,VSS,AW38,VSS,CM12
| |
| − | G3_TXN[6]/SATA36_TXN/XGBE32_TXN,M19,MC_DQS_H[15],CN47,MG0_ODT[0],AK9,P3_RXN[5],CG23,VDDCR_CPU,BW36,VSS,G16,VSS,AW42,VSS,CM15
| |
| − | G3_TXN[7]/SATA37_TXN/XGBE33_TXN,K20,MC_DQS_H[16],CW47,MG0_ODT[1],AG8,P3_RXN[6],CH22,VDDCR_CPU,BY21,VSS,G19,VSS,AW43,VSS,CM18
| |
| − | G3_TXN[8],L20,MC_DQS_H[17],AG46,MG1_CKE[0],BJ10,P3_RXN[7],CJ21,VDDCR_CPU,BY23,VSS,G22,VSS,AW44,VSS,CM21
| |
| − | G3_TXN[9],M22,MC_DQS_L[0],C47,MG1_CKE[1],BK10,P3_RXN[8],CG20,VDDCR_CPU,BY25,VSS,G25,VSS,AY18,VSS,CM24
| |
| − | G3_TXN[10],K23,MC_DQS_L[1],J47,MG1_CLK_H[0],AV9,P3_RXN[9],CH19,VDDCR_CPU,BY27,VSS,G28,VSS,AY20,VSS,CM27
| |
| − | G3_TXN[11],L23,MC_DQS_L[2],R47,MG1_CLK_H[1],AV10,P3_RXN[10],CJ18,VDDCR_CPU,BY29,VSS,G31,VSS,AY22,VSS,CM30
| |
| − | G3_TXN[12],M25,MC_DQS_L[3],AA47,MG1_CLK_L[0],AU8,P3_RXN[11],CG17,VDDCR_CPU,BY31,VSS,G34,VSS,AY24,VSS,CM33
| |
| − | G3_TXN[13],K26,MC_DQS_L[4],CA46,MG1_CLK_L[1],AU10,P3_RXN[12],CH16,VDDCR_CPU,BY33,VSS,G37,VSS,AY26,VSS,CM36
| |
| − | G3_TXN[14],L26,MC_DQS_L[5],CG46,MG1_CS_L[0],AN10,P3_RXN[13],CJ15,VDDCR_CPU,BY35,VSS,G40,VSS,AY30,VSS,CM39
| |
| − | G3_TXN[15],M28,MC_DQS_L[6],CN46,MG1_CS_L[1],AJ8,P3_RXN[14],CG14,VDDCR_CPU_SENSE,Y15,VSS,G43,VSS,AY32,VSS,CM42
| |
| − | G3_TXP[0]/SATA30_TXP/SATAE30_TXP0,L12,MC_DQS_L[7],CW46,MG1_ODT[0],AL10,P3_RXN[15],CH13,VDDCR_SOC,CA20,VSS,G45,VSS,AY34,VSS,CM45
| |
| − | G3_TXP[1]/SATA31_TXP/SATAE30_TXP1,K13,MC_DQS_L[8],AG47,MG1_ODT[1],AG10,P3_RXP[0],CG27,VDDCR_SOC,CA22,VSS,G48,VSS,AY36,VSS,CM47
| |
| − | G3_TXP[2]/SATA32_TXP/SATAE31_TXP0,M14,MC_DQS_L[9],D46,MG_ACT_L,BJ8,P3_RXP[1],CJ26,VDDCR_SOC,CA24,VSS,G50,VSS,BA19,VSS,CM49
| |
| − | G3_TXP[3]/SATA33_TXP/SATAE31_TXP1,L15,MC_DQS_L[10],K46,MG_ADD[0],AR8,P3_RXP[2],CH26,VDDCR_SOC,CA26,VSS,G52,VSS,BA21,VSS,CM52
| |
| − | G3_TXP[4]/SATA34_TXP/XGBE30_TXP,K16,MC_DQS_L[11],T46,MG_ADD[1],BB10,P3_RXP[3],CG24,VDDCR_SOC,CA28,VSS,G55,VSS,BA23,VSS,CM54
| |
| − | G3_TXP[5]/SATA35_TXP/XGBE31_TXP,M17,MC_DQS_L[12],AB46,MG_ADD[2],BB9,P3_RXP[4],CJ23,VDDCR_SOC,CB19,VSS,H1,VSS,BA25,VSS,CN2
| |
| − | G3_TXP[6]/SATA36_TXP/XGBE32_TXP,L18,MC_DQS_L[13],CB48,MG_ADD[3],BC8,P3_RXP[5],CH23,VDDCR_SOC,CB21,VSS,H4,VSS,BA29,VSS,CN4
| |
| − | G3_TXP[7]/SATA37_TXP/XGBE33_TXP,K19,MC_DQS_L[14],CH48,MG_ADD[4],BC10,P3_RXP[6],CG21,VDDCR_SOC,CB23,VSS,H6,VSS,BA31,VSS,CN7
| |
| − | G3_TXP[8],M20,MC_DQS_L[15],CP48,MG_ADD[5],BD9,P3_RXP[7],CJ20,VDDCR_SOC,CB25,VSS,H8,VSS,BA33,VSS,CN9
| |
| − | G3_TXP[9],L21,MC_DQS_L[16],CY48,MG_ADD[6],BD10,P3_RXP[8],CH20,VDDCR_SOC,CB27,VSS,H12,VSS,BA35,VSS,CN31
| |
| − | G3_TXP[10],K22,MC_DQS_L[17],AH46,MG_ADD[7],BE10,P3_RXP[9],CG18,VDDCR_SOC,CC11,VSS,H47,VSS,BA37,VSS,CN34
| |
| − | G3_TXP[11],M23,MC_EVENT_L,BG47,MG_ADD[8],BE8,P3_RXP[10],CJ17,VDDCR_SOC,CC13,VSS,H49,VSS,BA38,VSS,CN37
| |
| − | G3_TXP[12],L24,MC_PAROUT,BG46,MG_ADD[9],BF10,P3_RXP[11],CH17,VDDCR_SOC,CC16,VSS,H52,VSS,BB18,VSS,CN40
| |
| − | G3_TXP[13],K25,MC_RAS_L_ADD[16],BK48,MG_ADD[10],AP9,P3_RXP[12],CG15,VDDCR_SOC,CC18,VSS,H54,VSS,BB20,VSS,CN43
| |
| − | G3_TXP[14],M26,MC_RESET_L,AM46,MG_ADD[11],BF9,P3_RXP[13],CJ14,VDDCR_SOC,CC20,VSS,J2,VSS,BB22,VSS,CN45
| |
| − | G3_TXP[15],L27,MC_WE_L_ADD[14],BL47,MG_ADD[12],BG8,P3_RXP[14],CH14,VDDCR_SOC,CC22,VSS,J4,VSS,BB24,VSS,CN48
| |
| − | GPP_CLK0BN,DB20,MC_ZVSS,BB48,MG_ADD[13],AK10,P3_RXP[15],CG12,VDDCR_SOC,CC24,VSS,J7,VSS,BB26,VSS,CN50
| |
| − | GPP_CLK0BP,DA19,MD0_CKE[0],AN51,MG_ADD_17,AH9,P3_TXN[0],CR27,VDDCR_SOC,CC26,VSS,J9,VSS,BB28,VSS,CN52
| |
| − | GPP_CLK0TN,DB18,MD0_CKE[1],AM51,MG_ALERT_L,BG10,P3_TXN[1],CP26,VDDCR_SOC,CC28,VSS,J11,VSS,BB30,VSS,CN55
| |
| − | GPP_CLK0TP,DA18,MD0_CLK_H[0],BC51,MG_BANK[0],AP10,P3_TXN[2],CT25,VDDCR_SOC,CE11,VSS,J13,VSS,BB32,VSS,CP1
| |
| − | GPP_CLK1BN,B42,MD0_CLK_H[1],BC49,MG_BANK[1],AR10,P3_TXN[3],CR24,VDDCR_SOC,CE13,VSS,J16,VSS,BB34,VSS,CP4
| |
| − | GPP_CLK1BP,A41,MD0_CLK_L[0],BD51,MG_BG[0],BH9,P3_TXN[4],CP23,VDDCR_SOC,CE16,VSS,J19,VSS,BB36,VSS,CP6
| |
| − | GPP_CLK1TN,C41,MD0_CLK_L[1],BD50,MG_BG[1],BH10,P3_TXN[5],CT22,VDDCR_SOC,CE19,VSS,J22,VSS,BC19,VSS,CP8
| |
| − | GPP_CLK1TP,C40,MD0_CS_L[0],BL49,MG_CAS_L_ADD[15],AL8,P3_TXN[6],CR21,VDDCR_SOC,CE22,VSS,J25,VSS,BC21,VSS,CP11
| |
| − | GPP_CLK2BN,A37,MD0_CS_L[1],BP50,MG_CHECK[0],BU10,P3_TXN[7],CP20,VDDCR_SOC,CE25,VSS,J28,VSS,BC23,VSS,CP12
| |
| − | GPP_CLK2BP,B37,MD0_ODT[0],BN51,MG_CHECK[1],BU8,P3_TXN[8],CT19,VDDCR_SOC,CE28,VSS,J31,VSS,BC25,VSS,CP15
| |
| − | GPP_CLK2TN,C38,MD0_ODT[1],BT51,MG_CHECK[2],BN10,P3_TXN[9],CR18,VDDCR_SOC,CG11,VSS,J34,VSS,BC27,VSS,CP18
| |
| − | GPP_CLK2TP,C37,MD1_CKE[0],AP50,MG_CHECK[3],BN8,P3_TXN[10],CP17,VDDCR_SOC,CG13,VSS,J37,VSS,BC29,VSS,CP21
| |
| − | GPP_CLK3BN,DB35,MD1_CKE[1],AN49,MG_CHECK[4],BV10,P3_TXN[11],CT16,VDDCR_SOC,CG16,VSS,J40,VSS,BC31,VSS,CP24
| |
| − | GPP_CLK3BP,DA34,MD1_CLK_H[0],BE51,MG_CHECK[5],BV9,P3_TXN[12],CR15,VDDCR_SOC,CG19,VSS,J43,VSS,BC33,VSS,CP27
| |
| − | GPP_CLK3TN,CY36,MD1_CLK_H[1],BE49,MG_CHECK[6],BP10,P3_TXN[13],CP14,VDDCR_SOC,CG22,VSS,J45,VSS,BC35,VSS,CP30
| |
| − | GPP_CLK3TP,CY35,MD1_CLK_L[0],BF51,MG_CHECK[7],BP9,P3_TXN[14],CT13,VDDCR_SOC,CG25,VSS,J48,VSS,BC37,VSS,CP33
| |
| − | I2C0_SCL/EGPIO145/HP_SCL,DA40,MD1_CLK_L[1],BF50,MG_C[0],AF10,P3_TXN[15],CR12,VDDCR_SOC,CG28,VSS,J50,VSS,BC38,VSS,CP36
| |
| − | I2C0_SDA/EGPIO146/HP_SDA,DB41,MD1_CS_L[0],BK50,MG_C[1],AF9,P3_TXP[0],CP28,VDDCR_SOC,CJ11,VSS,J52,VSS,BD12,VSS,CP39
| |
| − | I2C1_SCL/EGPIO147/SFP_SCL,E22,MD1_CS_L[1],BP51,MG_C[2],AH10,P3_TXP[1],CR26,VDDCR_SOC,CJ13,VSS,J55,VSS,BD13,VSS,CP42
| |
| − | I2C1_SDA/EGPIO148/SFP_SDA,D22,MD1_ODT[0],BM50,MG_DATA[0],DB9,P3_TXP[2],CT26,VDDCR_SOC,CJ16,VSS,K1,VSS,BD14,VSS,CP45
| |
| − | I2C4_SCL/EGPIO149,CW43,MD1_ODT[1],BT50,MG_DATA[1],DA8,P3_TXP[3],CP25,VDDCR_SOC,CJ19,VSS,K4,VSS,BD18,VSS,CP47
| |
| − | I2C4_SDA/EGPIO150,CV44,MD_ACT_L,AP51,MG_DATA[2],CU10,P3_TXP[4],CR23,VDDCR_SOC,CJ22,VSS,K6,VSS,BD20,VSS,CP49
| |
| − | I2C5_SCL/EGPIO151,CV42,MD_ADD[0],BH51,MG_DATA[3],CU8,P3_TXP[5],CT23,VDDCR_SOC,CJ25,VSS,K8,VSS,BD22,VSS,CP52
| |
| − | I2C5_SDA/EGPIO152,CW42,MD_ADD[1],BA49,MG_DATA[4],DA10,P3_TXP[6],CP22,VDDCR_SOC,CJ28,VSS,K12,VSS,BD36,VSS,CP54
| |
| − | LAD0/EMMC_DAT0/EGPIO104,CV29,MD_ADD[2],BA51,MG_DATA[5],DB10,P3_TXP[7],CR20,VDDCR_SOC,CL11,VSS,K47,VSS,BE11,VSS,CR2
| |
| − | LAD1/EMMC_DAT1/EGPIO105,CW30,MD_ADD[3],AY51,MG_DATA[6],CV10,P3_TXP[8],CT20,VDDCR_SOC,CL13,VSS,K49,VSS,BE14,VSS,CR4
| |
| − | LAD2/EMMC_DAT2/EGPIO106,CV32,MD_ADD[4],AY50,MG_DATA[7],CV9,P3_TXP[9],CP19,VDDCR_SOC,CL16,VSS,K52,VSS,BE19,VSS,CR7
| |
| − | LAD3/EMMC_DAT3/EGPIO107,CW28,MD_ADD[5],AW51,MG_DATA[8],CR10,P3_TXP[10],CR17,VDDCR_SOC,CL19,VSS,K54,VSS,BE21,VSS,CR9
| |
| − | LFRAME_L/EMMC_DS/EGPIO109,CW27,MD_ADD[6],AW49,MG_DATA[9],CR8,P3_TXP[11],CT17,VDDCR_SOC,CL22,VSS,L2,VSS,BE35,VSS,CR31
| |
| − | LPCCLK0/EMMC_DAT4/EGPIO74,CV30,MD_ADD[7],AV50,MG_DATA[10],CL10,P3_TXP[12],CP16,VDDCR_SOC,CL25,VSS,L4,VSS,BE37,VSS,CR34
| |
| − | LPCCLK1/EMMC_DAT6/EGPIO75,CV33,MD_ADD[8],AV51,MG_DATA[11],CL8,P3_TXP[13],CR14,VDDCR_SOC,CL28,VSS,L7,VSS,BE38,VSS,CR37
| |
| − | LPC_CLKRUN_L/EMMC_DAT5/AGPIO88,CW31,MD_ADD[9],AU49,MG_DATA[12],CT10,P3_TXP[14],CT14,VDDCR_SOC,CN11,VSS,L9,VSS,BF13,VSS,CR40
| |
| − | LPC_PD_L/EMMC_CMD/AGPIO21,CV27,MD_ADD[10],BJ51,MG_DATA[13],CT9,P3_TXP[15],CP13,VDDCR_SOC,CN13,VSS,L11,VSS,BF18,VSS,CR43
| |
| − | LPC_PME_L/EMMC_PWR_CTRL/AGPIO22,CV26,MD_ADD[11],AU51,MG_DATA[14],CM10,PCIE_RST0_L/EGPIO26_0,DB27,VDDCR_SOC,CN16,VSS,L13,VSS,BF20,VSS,CR45
| |
| − | LPC_RST_L,CV24,MD_ADD[12],AT51,MG_DATA[15],CM9,PCIE_RST1_L/EGPIO26_1,A23,VDDCR_SOC,CN19,VSS,L16,VSS,BF22,VSS,CR48
| |
| − | LPC_SMI_L/NMI_SYNC_FLOOD_L/AGPIO86,CW34,MD_ADD[13],BN49,MG_DATA[16],CJ10,PCIE_RST2_L/EGPIO26_2,B28,VDDCR_SOC,CN22,VSS,L19,VSS,BF36,VSS,CR50
| |
| − | MA0_CKE[0],AN54,MD_ADD_17,BR51,MG_DATA[17],CJ8,PCIE_RST3_L/EGPIO26_3,DB21,VDDCR_SOC,CN25,VSS,L22,VSS,BG11,VSS,CR52
| |
| − | MA0_CKE[1],AN53,MD_ALERT_L,AT50,MG_DATA[18],CE10,PM_INTR_L/AGPIO89,CY44,VDDCR_SOC,CN28,VSS,L25,VSS,BG14,VSS,CR55
| |
| − | MA0_CLK_H[0],BB55,MD_BANK[0],BJ49,MG_DATA[19],CE8,PROCHOT_L,B22,VDDCR_SOC,CR11,VSS,L28,VSS,BG19,VSS,CT1
| |
| − | MA0_CLK_H[1],BD55,MD_BANK[1],BH50,MG_DATA[20],CK10,PWRGD_OUT,B30,VDDCR_SOC,CR13,VSS,L31,VSS,BG21,VSS,CT4
| |
| − | MA0_CLK_L[0],BC54,MD_BG[0],AR51,MG_DATA[21],CK9,PWROK,D12,VDDCR_SOC,CR16,VSS,L34,VSS,BG35,VSS,CT6
| |
| − | MA0_CLK_L[1],BE54,MD_BG[1],AR49,MG_DATA[22],CF10,PWR_BTN_L/AGPIO0,A29,VDDCR_SOC,CR19,VSS,L37,VSS,BG37,VSS,CT8
| |
| − | MA0_CS_L[0],BL53,MD_CAS_L_ADD[15],BM51,MG_DATA[23],CF9,PWR_GOOD,DB33,VDDCR_SOC,CR22,VSS,L40,VSS,BG38,VSS,CT11
| |
| − | MA0_CS_L[1],BR54,MD_CHECK[0],AF50,MG_DATA[24],CC10,REFCLK100SSC_N,AY28,VDDCR_SOC,CR25,VSS,L43,VSS,BH13,VSS,CT12
| |
| − | MA0_ODT[0],BM53,MD_CHECK[1],AF51,MG_DATA[25],CC8,REFCLK100SSC_P,BA27,VDDCR_SOC,CR28,VSS,L48,VSS,BH18,VSS,CT15
| |
| − | MA0_ODT[1],BT55,MD_CHECK[2],AK50,MG_DATA[26],BW10,RESET_L,B12,VDDCR_SOC,CV11,VSS,L50,VSS,BH20,VSS,CT18
| |
| − | MA1_CKE[0],AP53,MD_CHECK[3],AK51,MG_DATA[27],BW8,RSMRST_L,B39,VDDCR_SOC,CV13,VSS,L52,VSS,BH22,VSS,CT21
| |
| − | MA1_CKE[1],AM55,MD_CHECK[4],AE49,MG_DATA[28],CD10,RSVD,A32,VDDCR_SOC,CV16,VSS,L55,VSS,BH36,VSS,CT24
| |
| − | MA1_CLK_H[0],BD53,MD_CHECK[5],AE51,MG_DATA[29],CD9,RSVD,A40,VDDCR_SOC,CV19,VSS,M1,VSS,BJ11,VSS,CT27
| |
| − | MA1_CLK_H[1],BF55,MD_CHECK[6],AJ49,MG_DATA[30],BY10,RSVD,B33,VDDCR_SOC,CV22,VSS,M4,VSS,BJ14,VSS,CT30
| |
| − | MA1_CLK_L[0],BE53,MD_CHECK[7],AJ51,MG_DATA[31],BY9,RSVD,B40,VDDCR_SOC,CV25,VSS,M6,VSS,BJ19,VSS,CT33
| |
| − | MA1_CLK_L[1],BG54,MD_C[0],BU49,MG_DATA[32],AC8,RSVD,C19,VDDCR_SOC,CV28,VSS,M8,VSS,BJ21,VSS,CT36
| |
| − | MA1_CS_L[0],BL54,MD_C[1],BU51,MG_DATA[33],AC10,RSVD,D30,VDDCR_SOC,CY11,VSS,M12,VSS,BJ35,VSS,CT39
| |
| − | MA1_CS_L[1],BP55,MD_C[2],BR49,MG_DATA[34],W8,RSVD,D31,VDDCR_SOC,CY13,VSS,M47,VSS,BJ37,VSS,CT42
| |
| − | MA1_ODT[0],BN54,MD_DATA[0],A50,MG_DATA[35],W10,RSVD,D36,VDDCR_SOC,CY16,VSS,M49,VSS,BJ38,VSS,CT45
| |
| − | MA1_ODT[1],BU54,MD_DATA[1],B51,MG_DATA[36],AD9,RSVD,D37,VDDCR_SOC,CY19,VSS,M52,VSS,BK13,VSS,CT47
| |
| − | MA_ACT_L,AR53,MD_DATA[2],F50,MG_DATA[37],AD10,RSVD,D39,VDDCR_SOC,CY22,VSS,M54,VSS,BK15,VSS,CT49
| |
| − | MA_ADD[0],BH55,MD_DATA[3],F51,MG_DATA[38],Y9,RSVD,D40,VDDCR_SOC,CY25,VSS,N2,VSS,BK16,VSS,CT52
| |
| − | MA_ADD[1],AY55,MD_DATA[4],A49,MG_DATA[39],Y10,RSVD,E20,VDDCR_SOC,CY28,VSS,N4,VSS,BK17,VSS,CT54
| |
| − | MA_ADD[2],BA54,MD_DATA[5],B50,MG_DATA[40],U8,RSVD,E31,VDDCR_SOC_S5,CA30,VSS,N7,VSS,BK20,VSS,CU2
| |
| − | MA_ADD[3],BA53,MD_DATA[6],E49,MG_DATA[41],U10,RSVD,E32,VDDCR_SOC_S5,CB29,VSS,N9,VSS,BK22,VSS,CU4
| |
| − | MA_ADD[4],AY53,MD_DATA[7],E51,MG_DATA[42],N8,RSVD,E34,VDDCR_SOC_S5,CC30,VSS,N11,VSS,BK36,VSS,CU7
| |
| − | MA_ADD[5],AW54,MD_DATA[8],H50,MG_DATA[43],N10,RSVD,E35,VDDCR_SOC_S5_SENSE,CC32,VSS,N12,VSS,BK38,VSS,CU9
| |
| − | MA_ADD[6],AV55,MD_DATA[9],H51,MG_DATA[44],V9,RSVD,E37,VDDCR_SOC_SENSE,CB31,VSS,N13,VSS,BK39,VSS,CU11
| |
| − | MA_ADD[7],AV53,MD_DATA[10],M50,MG_DATA[45],V10,RSVD,E44,VDDIO_MEM_S3_ABCD,AM47,VSS,N14,VSS,BK40,VSS,CU12
| |
| − | MA_ADD[8],AW53,MD_DATA[11],M51,MG_DATA[46],P9,RSVD,F41,VDDIO_MEM_S3_ABCD,AM49,VSS,N15,VSS,BK41,VSS,CU13
| |
| − | MA_ADD[9],AT55,MD_DATA[12],G49,MG_DATA[47],P10,RSVD,F42,VDDIO_MEM_S3_ABCD,AM52,VSS,N16,VSS,BK42,VSS,CU14
| |
| − | MA_ADD[10],BH53,MD_DATA[13],G51,MG_DATA[48],L8,RSVD,G12,VDDIO_MEM_S3_ABCD,AM54,VSS,N17,VSS,BK43,VSS,CU15
| |
| − | MA_ADD[11],AU54,MD_DATA[14],L49,MG_DATA[49],L10,RSVD,G44,VDDIO_MEM_S3_ABCD,AN45,VSS,N18,VSS,BK44,VSS,CU16
| |
| − | MA_ADD[12],AU53,MD_DATA[15],L51,MG_DATA[50],G8,RSVD,U44,VDDIO_MEM_S3_ABCD,AN48,VSS,N19,VSS,BK45,VSS,CU17
| |
| − | MA_ADD[13],BN53,MD_DATA[16],P50,MG_DATA[51],G10,RSVD,BY19,VDDIO_MEM_S3_ABCD,AN50,VSS,N20,VSS,BL11,VSS,CU18
| |
| − | MA_ADD_17,BP53,MD_DATA[17],P51,MG_DATA[52],M9,RSVD,BY37,VDDIO_MEM_S3_ABCD,AN52,VSS,N21,VSS,BL14,VSS,CU19
| |
| − | MA_ALERT_L,AT53,MD_DATA[18],V50,MG_DATA[53],M10,RSVD,BY38,VDDIO_MEM_S3_ABCD,AP40,VSS,N22,VSS,BL17,VSS,CU20
| |
| − | MA_BANK[0],BJ53,MD_DATA[19],V51,MG_DATA[54],H9,RSVD,CA18,VDDIO_MEM_S3_ABCD,AP47,VSS,N23,VSS,BL18,VSS,CU21
| |
| − | MA_BANK[1],BJ54,MD_DATA[20],N49,MG_DATA[55],H10,RSVD,CN12,VDDIO_MEM_S3_ABCD,AP49,VSS,N24,VSS,BL19,VSS,CU22
| |
| − | MA_BG[0],AR54,MD_DATA[21],N51,MG_DATA[56],E8,RSVD,CN44,VDDIO_MEM_S3_ABCD,AP52,VSS,N25,VSS,BL21,VSS,CU23
| |
| − | MA_BG[1],AP55,MD_DATA[22],U49,MG_DATA[57],E10,RSVD,CV18,VDDIO_MEM_S3_ABCD,AP54,VSS,N26,VSS,BL35,VSS,CU24
| |
| − | MA_CAS_L_ADD[15],BM55,MD_DATA[23],U51,MG_DATA[58],B10,RSVD,CW18,VDDIO_MEM_S3_ABCD,AR41,VSS,N27,VSS,BL37,VSS,CU25
| |
| − | MA_CHECK[0],AE54,MD_DATA[24],Y50,MG_DATA[59],A10,RSVD,DA16,VDDIO_MEM_S3_ABCD,AR45,VSS,N28,VSS,BL38,VSS,CU26
| |
| − | MA_CHECK[1],AF55,MD_DATA[25],Y51,MG_DATA[60],F9,RTCCLK,E38,VDDIO_MEM_S3_ABCD,AR48,VSS,N29,VSS,BL40,VSS,CU27
| |
| − | MA_CHECK[2],AJ54,MD_DATA[26],AD50,MG_DATA[61],F10,S0A3_GPIO_0/AGPIO10_0/SGPIO0_CLK/MDIO0_SCL,DA28,VDDIO_MEM_S3_ABCD,AR50,VSS,N30,VSS,BL43,VSS,CU28
| |
| − | MA_CHECK[3],AK55,MD_DATA[27],AD51,MG_DATA[62],B9,S0A3_GPIO_1/EGPIO10_1/SGPIO1_CLK/MDIO2_SCL,E23,VDDIO_MEM_S3_ABCD,AR52,VSS,N31,VSS,BM1,VSS,CU29
| |
| − | MA_CHECK[4],AE53,MD_DATA[28],W49,MG_DATA[63],A9,S0A3_GPIO_2/EGPIO10_2/SGPIO2_CLK/MDIO4_SCL,E26,VDDIO_MEM_S3_ABCD,AR55,VSS,N32,VSS,BM2,VSS,CU30
| |
| − | MA_CHECK[5],AF53,MD_DATA[29],W51,MG_DQS_H[0],CW8,S0A3_GPIO_3/EGPIO10_3/SGPIO3_CLK/MDIO6_SCL,DA43,VDDIO_MEM_S3_ABCD,AT38,VSS,N33,VSS,BM3,VSS,CU31
| |
| − | MA_CHECK[6],AJ53,MD_DATA[30],AC49,MG_DQS_H[1],CN8,SA[0],D42,VDDIO_MEM_S3_ABCD,AT40,VSS,N34,VSS,BM4,VSS,CU32
| |
| − | MA_CHECK[7],AK53,MD_DATA[31],AC51,MG_DQS_H[2],CG8,SA[1],C43,VDDIO_MEM_S3_ABCD,AT47,VSS,N35,VSS,BM5,VSS,CU33
| |
| − | MA_C[0],BU53,MD_DATA[32],BY51,MG_DQS_H[3],CA8,SA[2],D44,VDDIO_MEM_S3_ABCD,AT49,VSS,N36,VSS,BM6,VSS,CU34
| |
| − | MA_C[1],BT53,MD_DATA[33],BY50,MG_DQS_H[4],AA10,SCL0/I2C2_SCL/EGPIO113/SPD_SCL,DA42,VDDIO_MEM_S3_ABCD,AT52,VSS,N37,VSS,BM7,VSS,CU35
| |
| − | MA_C[2],BR53,MD_DATA[34],CD51,MG_DQS_H[5],R10,SCL1/I2C3_SCL/AGPIO19/BMC_SCL,CW15,VDDIO_MEM_S3_ABCD,AT54,VSS,N38,VSS,BM8,VSS,CU36
| |
| − | MA_DATA[0],A53,MD_DATA[35],CD50,MG_DQS_H[6],J10,SDA0/I2C2_SDA/EGPIO114/SPD_SDA,DB42,VDDIO_MEM_S3_ABCD,AU41,VSS,N39,VSS,BM9,VSS,CU37
| |
| − | MA_DATA[1],B54,MD_DATA[36],BW51,MG_DQS_H[7],C10,SDA1/I2C3_SDA/AGPIO20/BMC_SDA,CV15,VDDIO_MEM_S3_ABCD,AU45,VSS,N40,VSS,BM10,VSS,CU38
| |
| − | MA_DATA[2],E54,MD_DATA[37],BW49,MG_DQS_H[8],BR8,SERIRQ/EMMC_DAT7/AGPIO87,CW33,VDDIO_MEM_S3_ABCD,AU48,VSS,N41,VSS,BM11,VSS,CU39
| |
| − | MA_DATA[3],F55,MD_DATA[38],CC51,MG_DQS_H[9],CY10,SIC,DA39,VDDIO_MEM_S3_ABCD,AU50,VSS,N42,VSS,BM13,VSS,CU40
| |
| − | MA_DATA[4],A52,MD_DATA[39],CC49,MG_DQS_H[10],CP10,SID,DB39,VDDIO_MEM_S3_ABCD,AU52,VSS,N43,VSS,BM16,VSS,CU41
| |
| − | MA_DATA[5],B53,MD_DATA[40],CF51,MG_DQS_H[11],CH10,SLP_S3_L,DA21,VDDIO_MEM_S3_ABCD,AV38,VSS,N44,VSS,BM18,VSS,CU42
| |
| − | MA_DATA[6],E53,MD_DATA[41],CF50,MG_DQS_H[12],CB10,SLP_S5_L,CY23,VDDIO_MEM_S3_ABCD,AV40,VSS,N45,VSS,BM20,VSS,CU43
| |
| − | MA_DATA[7],F53,MD_DATA[42],CK51,MG_DQS_H[13],AB9,SP3R1,C44,VDDIO_MEM_S3_ABCD,AV47,VSS,N48,VSS,BM22,VSS,CU44
| |
| − | MA_DATA[8],G54,MD_DATA[43],CK50,MG_DQS_H[14],T9,SP3R2,F12,VDDIO_MEM_S3_ABCD,AV49,VSS,N50,VSS,BM36,VSS,CU45
| |
| − | MA_DATA[9],H55,MD_DATA[44],CE51,MG_DQS_H[15],K9,SPI_CLK/ESPI_CLK,DB30,VDDIO_MEM_S3_ABCD,AV52,VSS,N52,VSS,BM38,VSS,CU48
| |
| − | MA_DATA[10],L54,MD_DATA[45],CE49,MG_DQS_H[16],D9,SPI_CS1_L/EGPIO118,DB32,VDDIO_MEM_S3_ABCD,AV54,VSS,N55,VSS,BM39,VSS,CU50
| |
| − | MA_DATA[11],M55,MD_DATA[46],CJ51,MG_DQS_H[17],BT10,SPI_CS2_L/ESPI_CS_L/EGPIO119,DA33,VDDIO_MEM_S3_ABCD,AW41,VSS,P1,VSS,BM42,VSS,CU52
| |
| − | MA_DATA[12],G53,MD_DATA[47],CJ49,MG_DQS_L[0],CY9,SPI_DI/ESPI_DAT1,DA30,VDDIO_MEM_S3_ABCD,AW45,VSS,P4,VSS,BM45,VSS,CU55
| |
| − | MA_DATA[13],H53,MD_DATA[48],CM51,MG_DQS_L[1],CP9,SPI_DO/ESPI_DAT0,CY32,VDDIO_MEM_S3_ABCD,AW48,VSS,P6,VSS,BN2,VSS,CV1
| |
| − | MA_DATA[14],L53,MD_DATA[49],CM50,MG_DQS_L[2],CH9,SPI_HOLD_L/ESPI_DAT3/EGPIO133,CY33,VDDIO_MEM_S3_ABCD,AW50,VSS,P8,VSS,BN4,VSS,CV4
| |
| − | MA_DATA[15],M53,MD_DATA[50],CT51,MG_DQS_L[3],CB9,SPI_TPM_CS_L/AGPIO76/PSP_ROM_CS_L,CY30,VDDIO_MEM_S3_ABCD,AW52,VSS,P12,VSS,BN7,VSS,CV6
| |
| − | MA_DATA[16],N54,MD_DATA[51],CT50,MG_DQS_L[4],AB10,SPI_WP_L/ESPI_DAT2/EGPIO122,DA31,VDDIO_MEM_S3_ABCD,AW55,VSS,P47,VSS,BN9,VSS,CV8
| |
| − | MA_DATA[17],P55,MD_DATA[52],CL51,MG_DQS_L[5],T10,SVC_CPU,A44,VDDIO_MEM_S3_ABCD,AY38,VSS,P49,VSS,BN11,VSS,CV31
| |
| − | MA_DATA[18],U54,MD_DATA[53],CL49,MG_DQS_L[6],K10,SVC_SOC,CV35,VDDIO_MEM_S3_ABCD,AY39,VSS,P52,VSS,BN14,VSS,CV34
| |
| − | MA_DATA[19],V55,MD_DATA[54],CR51,MG_DQS_L[7],D10,SVD_CPU,B44,VDDIO_MEM_S3_ABCD,AY42,VSS,P54,VSS,BN17,VSS,CV37
| |
| − | MA_DATA[20],N53,MD_DATA[55],CR49,MG_DQS_L[8],BT9,SVD_SOC,CV36,VDDIO_MEM_S3_ABCD,AY45,VSS,R2,VSS,BN18,VSS,CV40
| |
| − | MA_DATA[21],P53,MD_DATA[56],CV51,MG_DQS_L[9],CW10,SVT_CPU,A43,VDDIO_MEM_S3_ABCD,AY47,VSS,R4,VSS,BN19,VSS,CV43
| |
| − | MA_DATA[22],U53,MD_DATA[57],CV50,MG_DQS_L[10],CN10,SVT_SOC,CW37,VDDIO_MEM_S3_ABCD,AY49,VSS,R7,VSS,BN21,VSS,CV45
| |
| − | MA_DATA[23],V53,MD_DATA[58],DA49,MG_DQS_L[11],CG10,SYS_RESET_L/AGPIO1,A35,VDDIO_MEM_S3_ABCD,AY52,VSS,R9,VSS,BN35,VSS,CV47
| |
| − | MA_DATA[24],W54,MD_DATA[59],DB49,MG_DQS_L[12],CA10,TCK,B27,VDDIO_MEM_S3_ABCD,AY54,VSS,R11,VSS,BN37,VSS,CV49
| |
| − | MA_DATA[25],Y55,MD_DATA[60],CU51,MG_DQS_L[13],AA8,TDI,A25,VDDIO_MEM_S3_ABCD,BA40,VSS,R13,VSS,BN38,VSS,CV52
| |
| − | MA_DATA[26],AC54,MD_DATA[61],CU49,MG_DQS_L[14],R8,TDO,A26,VDDIO_MEM_S3_ABCD,BA43,VSS,R16,VSS,BN40,VSS,CV54
| |
| − | MA_DATA[27],AD55,MD_DATA[62],DA50,MG_DQS_L[15],J8,TEST4[0],CK34,VDDIO_MEM_S3_ABCD,BA45,VSS,R19,VSS,BN43,VSS,CW2
| |
| − | MA_DATA[28],W53,MD_DATA[63],DB50,MG_DQS_L[16],C8,TEST4[1],AC33,VDDIO_MEM_S3_ABCD,BA48,VSS,R22,VSS,BP4,VSS,CW4
| |
| − | MA_DATA[29],Y53,MD_DQS_H[0],D51,MG_DQS_L[17],BR10,TEST4[2],AC23,VDDIO_MEM_S3_ABCD,BA50,VSS,R25,VSS,BP6,VSS,CW7
| |
| − | MA_DATA[30],AC53,MD_DQS_H[1],K51,MG_EVENT_L,AT9,TEST4[3],CA21,VDDIO_MEM_S3_ABCD,BA52,VSS,R28,VSS,BP8,VSS,CW9
| |
| − | MA_DATA[31],AD53,MD_DQS_H[2],T51,MG_PAROUT,AT10,TEST5[0],CJ34,VDDIO_MEM_S3_ABCD,BB38,VSS,R31,VSS,BP11,VSS,CW11
| |
| − | MA_DATA[32],BW53,MD_DQS_H[3],AB51,MG_RAS_L_ADD[16],AN8,TEST5[1],AB34,VDDIO_MEM_S3_ABCD,BB39,VSS,R34,VSS,BP13,VSS,CW14
| |
| − | MA_DATA[33],BY53,MD_DQS_H[4],CB50,MG_RESET_L,BL10,TEST5[2],AB24,VDDIO_MEM_S3_ABCD,BB42,VSS,R37,VSS,BP16,VSS,CW17
| |
| − | MA_DATA[34],CC53,MD_DQS_H[5],CH50,MG_WE_L_ADD[14],AM9,TEST5[3],BY22,VDDIO_MEM_S3_ABCD,BB45,VSS,R40,VSS,BP18,VSS,CW20
| |
| − | MA_DATA[35],CD53,MD_DQS_H[6],CP50,MG_ZVSS,BA8,TEST6[0],CJ44,VDDIO_MEM_S3_ABCD,BB47,VSS,R43,VSS,BP20,VSS,CW23
| |
| − | MA_DATA[36],BW54,MD_DQS_H[7],CY50,MH0_CKE[0],BK5,TEST6[1],L45,VDDIO_MEM_S3_ABCD,BB49,VSS,R45,VSS,BP22,VSS,CW26
| |
| − | MA_DATA[37],BY55,MD_DQS_H[8],AH51,MH0_CKE[1],BL5,TEST6[2],U12,VDDIO_MEM_S3_ABCD,BB52,VSS,R48,VSS,BP36,VSS,CW29
| |
| − | MA_DATA[38],CC54,MD_DQS_H[9],C49,MH0_CLK_H[0],AY5,TEST6[3],CJ12,VDDIO_MEM_S3_ABCD,BB54,VSS,R50,VSS,BP38,VSS,CW32
| |
| − | MA_DATA[39],CD55,MD_DQS_H[10],J49,MH0_CLK_H[1],AY7,TEST31,D33,VDDIO_MEM_S3_ABCD,BC40,VSS,R52,VSS,BP39,VSS,CW35
| |
| − | MA_DATA[40],CE53,MD_DQS_H[11],R49,MH0_CLK_L[0],AW5,TEST40A,BC53,VDDIO_MEM_S3_ABCD,BC43,VSS,R55,VSS,BP42,VSS,CW38
| |
| − | MA_DATA[41],CF53,MD_DQS_H[12],AA49,MH0_CLK_L[1],AW6,TEST40B,BB43,VDDIO_MEM_S3_ABCD,BC45,VSS,T1,VSS,BP45,VSS,CW41
| |
| − | MA_DATA[42],CJ53,MD_DQS_H[13],CA51,MH0_CS_L[0],AM7,TEST40C,BB46,VDDIO_MEM_S3_ABCD,BC48,VSS,T4,VSS,BR2,VSS,CW44
| |
| − | MA_DATA[43],CK53,MD_DQS_H[14],CG51,MH0_CS_L[1],AJ6,TEST40D,BB50,VDDIO_MEM_S3_ABCD,BC50,VSS,T6,VSS,BR4,VSS,CW45
| |
| − | MA_DATA[44],CE54,MD_DQS_H[15],CN51,MH0_ODT[0],AK5,TEST40E,AY3,VDDIO_MEM_S3_ABCD,BC52,VSS,T8,VSS,BR7,VSS,CW48
| |
| − | MA_DATA[45],CF55,MD_DQS_H[16],CW51,MH0_ODT[1],AG5,TEST40F,BA13,VDDIO_MEM_S3_ABCD,BC55,VSS,T12,VSS,BR9,VSS,CW50
| |
| − | MA_DATA[46],CJ54,MD_DQS_H[17],AG49,MH1_CKE[0],BJ6,TEST40G,BA10,VDDIO_MEM_S3_ABCD,BD38,VSS,T47,VSS,BR11,VSS,CW52
| |
| − | MA_DATA[47],CK55,MD_DQS_L[0],C51,MH1_CKE[1],BK7,TEST40H,BA6,VDDIO_MEM_S3_ABCD,BD39,VSS,T49,VSS,BR14,VSS,CW55
| |
| − | MA_DATA[48],CL53,MD_DQS_L[1],J51,MH1_CLK_H[0],AV5,TEST41[0],CY26,VDDIO_MEM_S3_ABCD,BD42,VSS,T52,VSS,BR17,VSS,CY1
| |
| − | MA_DATA[49],CM53,MD_DQS_L[2],R51,MH1_CLK_H[1],AV7,TEST41[1],D34,VDDIO_MEM_S3_ABCD,BD45,VSS,T54,VSS,BR18,VSS,CY4
| |
| − | MA_DATA[50],CR53,MD_DQS_L[3],AA51,MH1_CLK_L[0],AU5,TEST41[2],B16,VDDIO_MEM_S3_ABCD,BD47,VSS,U2,VSS,BR19,VSS,CY6
| |
| − | MA_DATA[51],CT53,MD_DQS_L[4],CA49,MH1_CLK_L[1],AU6,TEST41[3],CY20,VDDIO_MEM_S3_ABCD,BD49,VSS,U4,VSS,BR21,VSS,CY8
| |
| − | MA_DATA[52],CL54,MD_DQS_L[5],CG49,MH1_CS_L[0],AN6,TEST47[0],CW36,VDDIO_MEM_S3_ABCD,BD52,VSS,U7,VSS,BR35,VSS,CY31
| |
| − | MA_DATA[53],CM55,MD_DQS_L[6],CN49,MH1_CS_L[1],AJ5,TEST47[1],E29,VDDIO_MEM_S3_ABCD,BD54,VSS,U9,VSS,BR37,VSS,CY34
| |
| − | MA_DATA[54],CR54,MD_DQS_L[7],CW49,MH1_ODT[0],AL6,TEST47[2],D18,VDDIO_MEM_S3_ABCD,BE40,VSS,U11,VSS,BR38,VSS,CY37
| |
| − | MA_DATA[55],CT55,MD_DQS_L[8],AG51,MH1_ODT[1],AG6,TEST47[3],CW21,VDDIO_MEM_S3_ABCD,BE43,VSS,U13,VSS,BR40,VSS,CY40
| |
| − | MA_DATA[56],CU53,MD_DQS_L[9],D50,MH_ACT_L,BJ5,THERMTRIP_L,A28,VDDIO_MEM_S3_ABCD,BE45,VSS,U16,VSS,BR43,VSS,CY43
| |
| − | MA_DATA[57],CV53,MD_DQS_L[10],K50,MH_ADD[0],AR5,TMS,C26,VDDIO_MEM_S3_ABCD,BE48,VSS,U19,VSS,BT1,VSS,CY45
| |
| − | MA_DATA[58],DB53,MD_DQS_L[11],T50,MH_ADD[1],BB7,TRST_L,C25,VDDIO_MEM_S3_ABCD,BE50,VSS,U22,VSS,BT4,VSS,CY47
| |
| − | MA_DATA[59],DB52,MD_DQS_L[12],AB50,MH_ADD[2],BB5,UART0_CTS_L/UART2_RXD/EGPIO135,CV41,VDDIO_MEM_S3_ABCD,BE52,VSS,U25,VSS,BT6,VSS,CY49
| |
| − | MA_DATA[60],CU54,MD_DQS_L[13],CB51,MH_ADD[3],BC5,UART0_INTR/AGPIO139,CV38,VDDIO_MEM_S3_ABCD,BF38,VSS,U28,VSS,BT8,VSS,CY52
| |
| − | MA_DATA[61],CV55,MD_DQS_L[14],CH51,MH_ADD[4],BC6,UART0_RTS_L/UART2_TXD/EGPIO137,CW40,VDDIO_MEM_S3_ABCD,BF39,VSS,U31,VSS,BT11,VSS,CY54
| |
| − | MA_DATA[62],DA54,MD_DQS_L[15],CP51,MH_ADD[5],BD5,UART0_RXD/EGPIO136,CV39,VDDIO_MEM_S3_ABCD,BF42,VSS,U34,VSS,BT13,VSS,DA4
| |
| − | MA_DATA[63],DA53,MD_DQS_L[16],CY51,MH_ADD[6],BD7,UART0_TXD/EGPIO138,CW39,VDDIO_MEM_S3_ABCD,BF45,VSS,U37,VSS,BT16,VSS,DA7
| |
| − | MA_DQS_H[0],D55,MD_DQS_L[17],AH50,MH_ADD[7],BE6,UART1_CTS_L/UART3_TXD/EGPIO140,CY38,VDDIO_MEM_S3_ABCD,BF47,VSS,U40,VSS,BT18,VSS,DA9
| |
| − | MA_DQS_H[1],K55,MD_EVENT_L,BG51,MH_ADD[8],BE5,UART1_INTR/AGPIO144,DA36,VDDIO_MEM_S3_ABCD,BF49,VSS,U43,VSS,BT20,VSS,DA11
| |
| − | MA_DQS_H[2],T55,MD_PAROUT,BG49,MH_ADD[9],BF7,UART1_RTS_L/UART3_RXD/EGPIO142,DB38,VDDIO_MEM_S3_ABCD,BF52,VSS,U45,VSS,BT22,VSS,DA12
| |
| − | MA_DQS_H[3],AB55,MD_RAS_L_ADD[16],BK51,MH_ADD[10],AP5,UART1_RXD/EGPIO141,DB36,VDDIO_MEM_S3_ABCD,BF54,VSS,U48,VSS,BT36,VSS,DA14
| |
| − | MA_DQS_H[4],CB53,MD_RESET_L,AM50,MH_ADD[11],BF5,UART1_TXD/EGPIO143,DA37,VDDIO_MEM_S3_ABCD,BG40,VSS,U50,VSS,BT38,VSS,DA17
| |
| − | MA_DQS_H[5],CH53,MD_WE_L_ADD[14],BL51,MH_ADD[12],BG5,USB0_0_ZVSS,DB12,VDDIO_MEM_S3_ABCD,BG43,VSS,U52,VSS,BT39,VSS,DA20
| |
| − | MA_DQS_H[6],CP53,MD_ZVSS,BB51,MH_ADD[13],AK7,USB1_0_ZVSS,CY12,VDDIO_MEM_S3_ABCD,BG45,VSS,U55,VSS,BT42,VSS,DA23
| |
| − | MA_DQS_H[7],CY53,ME0_CKE[0],BK2,MH_ADD_17,AH5,USB2_1_ZVSS,D16,VDDIO_MEM_S3_ABCD,BG48,VSS,V1,VSS,BT45,VSS,DA26
| |
| − | MA_DQS_H[8],AH55,ME0_CKE[1],BK3,MH_ALERT_L,BG6,USB3_1_ZVSS,E16,VDDIO_MEM_S3_ABCD,BG50,VSS,V4,VSS,BU2,VSS,DA29
| |
| − | MA_DQS_H[9],C53,ME0_CLK_H[0],BA1,MH_BANK[0],AP7,USB_0_HSD0N,CY18,VDDIO_MEM_S3_ABCD,BG52,VSS,V6,VSS,BU4,VSS,DA32
| |
| − | MA_DQS_H[10],J53,ME0_CLK_H[1],AW1,MH_BANK[1],AR6,USB_0_HSD0P,CY17,VDDIO_MEM_S3_ABCD,BG55,VSS,V8,VSS,BU7,VSS,DA35
| |
| − | MA_DQS_H[11],R53,ME0_CLK_L[0],AY2,MH_BG[0],BH5,USB_0_HSD1N,CV17,VDDIO_MEM_S3_ABCD,BH38,VSS,V12,VSS,BU9,VSS,DA38
| |
| − | MA_DQS_H[12],AA53,ME0_CLK_L[1],AV2,MH_BG[1],BH7,USB_0_HSD1P,CW16,VDDIO_MEM_S3_ABCD,BH39,VSS,V47,VSS,BU11,VSS,DA41
| |
| − | MA_DQS_H[13],CA54,ME0_CS_L[0],AM3,MH_CAS_L_ADD[15],AL5,USB_0_SS_0RXN,DB15,VDDIO_MEM_S3_ABCD,BH42,VSS,V49,VSS,BU14,VSS,DA44
| |
| − | MA_DQS_H[14],CG54,ME0_CS_L[1],AH2,MH_CHECK[0],BU6,USB_0_SS_0RXP,DA15,VDDIO_MEM_S3_ABCD,BH45,VSS,V52,VSS,BU17,VSS,DA45
| |
| − | MA_DQS_H[15],CN54,ME0_ODT[0],AL3,MH_CHECK[1],BU5,USB_0_SS_0TXN,CV14,VDDIO_MEM_S3_ABCD,BH47,VSS,V54,VSS,BU18,VSS,DA48
| |
| − | MA_DQS_H[16],CW54,ME0_ODT[1],AG1,MH_CHECK[2],BN6,USB_0_SS_0TXP,CW13,VDDIO_MEM_S3_ABCD,BH49,VSS,W2,VSS,BU19,VSS,DA51
| |
| − | MA_DQS_H[17],AG53,ME1_CKE[0],BJ3,MH_CHECK[3],BN5,USB_0_SS_1RXN,DB14,VDDIO_MEM_S3_ABCD,BH52,VSS,W4,VSS,BU21,VSS,DA52
| |
| − | MA_DQS_L[0],C54,ME1_CKE[1],BL1,MH_CHECK[4],BV7,USB_0_SS_1RXP,DA13,VDDIO_MEM_S3_ABCD,BH54,VSS,W7,VSS,BU35,VSS,DB5
| |
| − | MA_DQS_L[1],J54,ME1_CLK_H[0],AW3,MH_CHECK[5],BV5,USB_0_SS_1TXN,CW12,VDDIO_MEM_S3_ABCD,BJ40,VSS,W9,VSS,BU37,VSS,DB8
| |
| − | MA_DQS_L[2],R54,ME1_CLK_H[1],AU1,MH_CHECK[6],BP7,USB_0_SS_1TXP,CV12,VDDIO_MEM_S3_ABCD,BJ43,VSS,W11,VSS,BU38,VSS,DB11
| |
| − | MA_DQS_L[3],AA54,ME1_CLK_L[0],AV3,MH_CHECK[7],BP5,USB_1_HSD2N,C17,VDDIO_MEM_S3_ABCD,BJ45,VSS,W13,VSS,BU40,VSS,DB13
| |
| − | MA_DQS_L[4],CA53,ME1_CLK_L[1],AT2,MH_C[0],AF7,USB_1_HSD2P,C16,VDDIO_MEM_S3_ABCD,BJ48,VSS,W16,VSS,BU43,VSS,DB16
| |
| − | MA_DQS_L[5],CG53,ME1_CS_L[0],AM2,MH_C[1],AF5,USB_1_HSD3N,B18,VDDIO_MEM_S3_ABCD,BJ50,VSS,W19,VSS,BV4,VSS,DB19
| |
| − | MA_DQS_L[6],CN53,ME1_CS_L[1],AJ1,MH_C[2],AH7,USB_1_HSD3P,A17,VDDIO_MEM_S3_ABCD,BJ52,VSS,W22,VSS,BV6,VSS,DB22
| |
| − | MA_DQS_L[7],CW53,ME1_ODT[0],AK2,MH_DATA[0],DB6,USB_1_SS_2RXN,E13,VDDIO_MEM_S3_ABCD,BK47,VSS,W25,VSS,BV8,VSS,DB25
| |
| − | MA_DQS_L[8],AG54,ME1_ODT[1],AF2,MH_DATA[1],DA5,USB_1_SS_2RXP,D13,VDDIO_MEM_S3_ABCD,BK49,VSS,W28,VSS,BV11,VSS,DB28
| |
| − | MA_DQS_L[9],D53,ME_ACT_L,BH3,MH_DATA[2],CU6,USB_1_SS_2TXN,A13,VDDIO_MEM_S3_ABCD,BK52,VSS,W31,VSS,BV13,VSS,DB31
| |
| − | MA_DQS_L[10],K53,ME_ADD[0],AR1,MH_DATA[3],CU5,USB_1_SS_2TXP,B13,VDDIO_MEM_S3_ABCD,BK54,VSS,W34,VSS,BV16,VSS,DB34
| |
| − | MA_DQS_L[11],T53,ME_ADD[1],BC1,MH_DATA[4],DB7,USB_1_SS_3RXN,D15,VDDIO_MEM_S3_ABCD,BL45,VSS,W37,VSS,BV18,VSS,DB37
| |
| − | MA_DQS_L[12],AB53,ME_ADD[2],BB2,MH_DATA[5],DA6,USB_1_SS_3RXP,E14,VDDIO_MEM_S3_ABCD,BL48,VSS,W40,VSS,BV20,VSS,DB40
| |
| − | MA_DQS_L[13],CB55,ME_ADD[3],BB3,MH_DATA[6],CV7,USB_1_SS_3TXN,B15,VDDIO_MEM_S3_ABCD,BL50,VSS,W43,VSS,BV22,VSS,DB43
| |
| − | MA_DQS_L[14],CH55,ME_ADD[4],BC3,MH_DATA[7],CV5,USB_1_SS_3TXP,A14,VDDIO_MEM_S3_ABCD,BL52,VSS,W45,VSS,BV36,VSS,DB45
| |
| − | MA_DQS_L[15],CP55,ME_ADD[5],BD2,MH_DATA[8],CR6,USB_OC0_L/AGPIO16_0,CY15,VDDIO_MEM_S3_ABCD,BL55,VSS,W48,VSS,BV38,VSS,DB48
| |
| − | MA_DQS_L[16],CY55,ME_ADD[6],BE1,MH_DATA[9],CR5,USB_OC1_L/AGPIO17_0,CY14,VDDIO_MEM_S3_ABCD,BM47,VSS,W50,VSS,BV39,VSS,DB51
| |
| − | MA_DQS_L[17],AH53,ME_ADD[7],BE3,MH_DATA[10],CL6,USB_OC2_L/EGPIO16_1,C13,VDDIO_MEM_S3_ABCD,BM49,VSS,W52,VSS,BV42,VSS_SENSE_A,Y14
| |
| − | MA_EVENT_L,BF53,ME_ADD[8],BD3,MH_DATA[11],CL5,USB_OC3_L/EGPIO17_1,C14,VDDIO_MEM_S3_ABCD,BM52,VSS,W55,VSS,BV45,VSS_SENSE_B,CB32
| |
| − | MA_PAROUT,BG53,ME_ADD[9],BG1,MH_DATA[12],CT7,VDDBT_RTC_G,CB34,VDDIO_MEM_S3_ABCD,BM54,VSS,Y1,VSS,BV46,WAFL0_ZVSS,CY21
| |
| − | MA_RAS_L_ADD[16],BK55,ME_ADD[10],AR3,MH_DATA[13],CT5,VDDCR_CPU,B11,VDDIO_MEM_S3_ABCD,BN45,VSS,Y4,VSS,BV47,WAFL1_ZVSS,A16
| |
| − | MA_RESET_L,AM53,ME_ADD[11],BF2,MH_DATA[14],CM7,VDDCR_CPU,B14,VDDIO_MEM_S3_ABCD,BN48,VSS,Y6,VSS,BV48,WAFL2_ZVSS,C28
| |
| − | MA_WE_L_ADD[14],BK53,ME_ADD[12],BF3,MH_DATA[15],CM5,VDDCR_CPU,B17,VDDIO_MEM_S3_ABCD,BN50,VSS,Y8,VSS,BV49,WAFL3_ZVSS,DB17
| |
| − | MA_ZVSS,BB53,ME_ADD[13],AK3,MH_DATA[16],CJ6,VDDCR_CPU,B20,VDDIO_MEM_S3_ABCD,BN52,VSS,Y11,VSS,BV50,WAFL_RXN[0],B34
| |
| − | MB0_CKE[0],AR40,ME_ADD_17,AJ3,MH_DATA[17],CJ5,VDDCR_CPU,B23,VDDIO_MEM_S3_ABCD,BP47,VSS,Y12,VSS,BV51,WAFL_RXN[1],C34
| |
| − | MB0_CKE[1],AP41,ME_ALERT_L,BG3,MH_DATA[18],CE6,VDDCR_CPU,B26,VDDIO_MEM_S3_ABCD,BP49,VSS,Y16,VSS,BV52,WAFL_RXP[0],A34
| |
| − | MB0_CLK_H[0],BC44,ME_BANK[0],AP3,MH_DATA[19],CE5,VDDCR_CPU,B29,VDDIO_MEM_S3_ABCD,BP52,VSS,Y18,VSS,BV53,WAFL_RXP[1],C35
| |
| − | MB0_CLK_H[1],BC42,ME_BANK[1],AP2,MH_DATA[20],CK7,VDDCR_CPU,B32,VDDIO_MEM_S3_ABCD,BP54,VSS,Y20,VSS,BV54,WAFL_TXN[0],C32
| |
| − | MB0_CLK_L[0],BD44,ME_BG[0],BH2,MH_DATA[21],CK5,VDDCR_CPU,B35,VDDIO_MEM_S3_ABCD,BR45,VSS,Y22,VSS,BV55,WAFL_TXN[1],A31
| |
| − | MB0_CLK_L[1],BD43,ME_BG[1],BJ1,MH_DATA[22],CF7,VDDCR_CPU,B38,VDDIO_MEM_S3_ABCD,BR48,VSS,Y24,VSS,BW2,WAFL_TXP[0],C31
| |
| − | MB0_CS_L[0],BF44,ME_CAS_L_ADD[15],AL1,MH_DATA[23],CF5,VDDCR_CPU,B41,VDDIO_MEM_S3_ABCD,BR50,VSS,Y26,VSS,BW4,WAFL_TXP[1],B31
| |
| − | MB0_CS_L[1],BH44,ME_CHECK[0],BV2,MH_DATA[24],CC6,VDDCR_CPU,B43,VDDIO_MEM_S3_ABCD,BR52,VSS,Y28,VSS,BW7,WAKE_L/AGPIO2,B36
| |
| − | MB0_ODT[0],BG44,ME_CHECK[1],BU1,MH_DATA[25],CC5,VDDCR_CPU,B45,VDDIO_MEM_S3_ABCD,BR55,VSS,Y30,VSS,BW9,X32K_X1,DA25
| |
| − | MB0_ODT[1],BJ44,ME_CHECK[2],BP2,MH_DATA[26],BW6,VDDCR_CPU,D11,VDDIO_MEM_S3_ABCD,BT47,VSS,Y32,VSS,BW11,X32K_X2,DB26
| |
| − | MB1_CKE[0],AT39,ME_CHECK[3],BN1,MH_DATA[27],BW5,VDDCR_CPU,D14,VDDIO_MEM_S3_ABCD,BT49,VSS,Y34,VSS,BW14,X48M_X1,DA22
| |
| − | MB1_CKE[1],AR39,ME_CHECK[4],BV3,MH_DATA[28],CD7,VDDCR_CPU,D17,VDDIO_MEM_S3_ABCD,BT52,VSS,Y36,VSS,BW17,X48M_X2,DB23
| |
| − | MB1_CLK_H[0],BB41,ME_CHECK[5],BU3,MH_DATA[29],CD5,VDDCR_CPU,D20,VDDIO_MEM_S3_ABCD,BT54,VSS,Y38,VSS,BW18,X156M_H[0],CW22
| |
| − | MB1_CLK_H[1],BB40,ME_CHECK[6],BP3,MH_DATA[30],BY7,VDDCR_CPU,D23,VDDIO_MEM_S3_ABCD,BU45,VSS,Y39,VSS,BW19,X156M_H[1],E43
| |
| − | MB1_CLK_L[0],BC41,ME_CHECK[7],BN3,MH_DATA[31],BY5,VDDCR_CPU,D26,VDDIO_MEM_S3_ABCD,BU48,VSS,Y40,VSS,BW21,X156M_H[2],D19
| |
| − | MB1_CLK_L[1],BC39,ME_C[0],AF3,MH_DATA[32],AC5,VDDCR_CPU,D29,VDDIO_MEM_S3_ABCD,BU50,VSS,Y41,VSS,BW35,X156M_H[3],CW19
| |
| − | MB1_CS_L[0],BF40,ME_C[1],AG3,MH_DATA[33],AC6,VDDCR_CPU,D32,VDDIO_MEM_S3_ABCD,BU52,VSS,Y42,VSS,BW37,X156M_L[0],CV23
| |
| − | MB1_CS_L[1],BH41,ME_C[2],AH3,MH_DATA[34],W5,VDDCR_CPU,D35,VDDIO_MEM_S3_ABCD_FB_H,AP38,VSS,Y43,VSS,BW38,X156M_L[1],F44
| |
| − | MB1_ODT[0],BG39,ME_DATA[0],DB3,MH_DATA[35],W6,VDDCR_CPU,D38,VDDIO_MEM_S3_ABCD_FB_L,AN38,VSS,Y44,VSS,BW40,X156M_L[2],E19
| |
| − | MB1_ODT[1],BJ41,ME_DATA[1],DA2,MH_DATA[36],AD5,VDDCR_CPU,D41,VDDIO_MEM_S3_EFGH,AF4,VSS,Y45,VSS,BW43,X156M_L[3],CV20
| |
| − | MB_ACT_L,AT41,ME_DATA[2],CV2,MH_DATA[37],AD7,VDDCR_CPU,D43,VDDIO_MEM_S3_EFGH,AF6,VSS,Y47,VSS,BW45,XTRIG_L[4],B21
| |
| − | MB_ADD[0],BE41,ME_DATA[3],CU1,MH_DATA[38],Y5,VDDCR_CPU,D45,VDDIO_MEM_S3_EFGH,AF8,VSS,Y49,VSS,BW48,XTRIG_L[5],A20
| |
| − | MB_ADD[1],BA44,ME_DATA[4],DB4,MH_DATA[39],Y7,VDDCR_CPU,F11,VDDIO_MEM_S3_EFGH,AF11,VSS,Y52,VSS,BW50,XTRIG_L[6],A19
| |
| − | MB_ADD[2],BA41,ME_DATA[5],DA3,MH_DATA[40],U5,VDDCR_CPU,F14,VDDIO_MEM_S3_EFGH,AG2,VSS,Y54,VSS,BW52,XTRIG_L[7],B19
| |
| − | MB_ADD[3],BA39,ME_DATA[6],CV3,MH_DATA[41],U6,VDDCR_CPU,F17,VDDIO_MEM_S3_EFGH,AG4,VSS,AA2,VSS,BW55
| |
| − | MB_ADD[4],BA42,ME_DATA[7],CU3,MH_DATA[42],N5,VDDCR_CPU,F20,VDDIO_MEM_S3_EFGH,AG7,VSS,AA4,VSS,BY1
| |
| − | -->
| |
| − |
| |
| − | === Pin Description ===
| |
| − | Socket SP3, {{\\|Socket sTRX4|sTRX4}}, and {{\\|Socket sWRX8|sWRX8}} have the same pinout with some constraints as noted.
| |
| − |
| |
| − | {| class="wikitable sortable"
| |
| − | !Signal!!Type!!Description
| |
| − | |-
| |
| − | |MA-MD_ACT_L||O-IOMEM_ABCD-S||DRAM Channel A-D<ref name="memch">Only memory channels A, D, E, and H are available on {{\\|Socket sTRX4}}.</ref> Activation Command
| |
| − | |-
| |
| − | |MA-MD_ADD[13:0]||O-IOMEM_ABCD-S||DRAM Column/Row Address
| |
| − | |-
| |
| − | |MA-MD_ADD_17||O-IOMEM_ABCD-S||DRAM Column/Row Address 17
| |
| − | |-
| |
| − | |MA-MD_ALERT_L||I-IOMEM_ABCD-S||DRAM Alert (CRC error and Command/Address parity error)
| |
| − | |-
| |
| − | |MA-MD_BANK[1:0]||O-IOMEM_ABCD-S||DRAM Bank Address
| |
| − | |-
| |
| − | |MA-MD_BG[1:0]||O-IOMEM_ABCD-S||DRAM Bank Group
| |
| − | |-
| |
| − | |MA-MD_CAS_L_ADD[15]||O-IOMEM_ABCD-S||DRAM Column Address Strobe or Column/Row Address 15
| |
| − | |-
| |
| − | |MA-MD_CHECK[7:0]||B-IOMEM_ABCD-S||DRAM ECC Check Bits
| |
| − | |-
| |
| − | |MA-MD_C[2:0]||O-IOMEM_ABCD-S||DRAM Chip ID Signals
| |
| − | |-
| |
| − | |MA-MD_DATA[63:0]||B-IOMEM_ABCD-S||DRAM Data Bus
| |
| − | |-
| |
| − | |MA-MD_DQS_H/L[8:0]||B-IOMEM_ABCD-S||DRAM Differential Data Strobe
| |
| − | |-
| |
| − | |MA-MD_DQS_H[17:9]||B-IOMEM_ABCD-S||DRAM Differential Data Strobe for RDIMMs, DM[8:0] Data Mask output for UDIMMs<ref name="memtype">{{abbr|UDIMM}}s are not supported on Socket SP3. {{abbr|RDIMM}}s are not supported on Socket sTRX4.</ref>
| |
| − | |-
| |
| − | |MA-MD_DQS_L[17:9]||B-IOMEM_ABCD-S||DRAM Differential Data Strobe for RDIMMs, not connected for UDIMMs
| |
| − | |-
| |
| − | |MA-MD_EVENT_L||I-IOMEM_ABCD-S||DRAM Thermal Event
| |
| − | |-
| |
| − | |MA-MD_PAROUT||O-IOMEM_ABCD-S||DRAM Command and Address Parity
| |
| − | |-
| |
| − | |MA-MD_RAS_L_ADD[16]||O-IOMEM_ABCD-S||DRAM Row Address Strobe or Column/Row Address 16
| |
| − | |-
| |
| − | |MA-MD_RESET_L||O-IOMEM_ABCD-S||DRAM Reset
| |
| − | |-
| |
| − | |MA-MD_WE_L_ADD[14]||O-IOMEM_ABCD-S||DRAM Write Enable or Column/Row Address 14
| |
| − | |-
| |
| − | |MA-MD_ZVSS||A||DRAM Interface Drive-Strength Auto-Compensation Resistor to VSS
| |
| − | |-
| |
| − | |MA0-MD0_CKE[1:0]<br/>MA1-MD1_CKE[1:0]||O-IOMEM_ABCD-S||DRAM Channel A-D DIMM 0-1 Clock Enable
| |
| − | |-
| |
| − | |MA0-MD0_CLK_H/L[1:0]<br/>MA1-MD1_CLK_H/L[1:0]||O-IOMEM_ABCD-D||DRAM Channel A-D DIMM 0-1 Differential Clock
| |
| − | |-
| |
| − | |MA0-MD0_CS_L[1:0]<br/>MA1-MD1_CS_L[1:0]||O-IOMEM_ABCD-S||DRAM Channel A-D DIMM 0-1 Chip Select
| |
| − | |-
| |
| − | |MA0-MD0_ODT[1:0]<br/>MA1-MD1_ODT[1:0]||O-IOMEM_ABCD-S||DRAM Channel A-D DIMM 0-1 Enable Pin for On Die Termination
| |
| − | |-
| |
| − | |ME-MH_ACT_L||O-IOMEM_EFGH-S||DRAM Channel E-H<ref name="memch"/> Activation Command
| |
| − | |-
| |
| − | |ME-MH_ADD[13:0]||O-IOMEM_EFGH-S||DRAM Column/Row Address
| |
| − | |-
| |
| − | |ME-MH_ADD_17||O-IOMEM_EFGH-S||DRAM Column/Row Address 17
| |
| − | |-
| |
| − | |ME-MH_ALERT_L||I-IOMEM_EFGH-S||DRAM Alert (CRC error and Command/Address parity error)
| |
| − | |-
| |
| − | |ME-MH_BANK[1:0]||O-IOMEM_EFGH-S||DRAM Bank Address
| |
| − | |-
| |
| − | |ME-MH_BG[1:0]||O-IOMEM_EFGH-S||DRAM Bank Group
| |
| − | |-
| |
| − | |ME-MH_CAS_L_ADD[15]||O-IOMEM_EFGH-S||DRAM Column Address Strobe or Column/Row Address 15
| |
| − | |-
| |
| − | |ME-MH_CHECK[7:0]||B-IOMEM_EFGH-S||DRAM ECC Check Bits
| |
| − | |-
| |
| − | |ME-MH_C[2:0]||O-IOMEM_EFGH-S||DRAM Chip ID Signals
| |
| − | |-
| |
| − | |ME-MH_DATA[63:0]||B-IOMEM_EFGH-S||DRAM Data Bus
| |
| − | |-
| |
| − | |ME-MH_DQS_H/L[8:0]||B-IOMEM_EFGH-S||DRAM Differential Data Strobe
| |
| − | |-
| |
| − | |ME-MH_DQS_H[17:9]||B-IOMEM_EFGH-S||DRAM Differential Data Strobe for RDIMMs, DM[8:0] Data Mask output for UDIMMs<ref name="memtype"/>
| |
| − | |-
| |
| − | |ME-MH_DQS_L[17:9]||B-IOMEM_EFGH-S||DRAM Differential Data Strobe for RDIMMs, not connected for UDIMMs
| |
| − | |-
| |
| − | |ME-MH_EVENT_L||I-IOMEM_EFGH-S||DRAM Thermal Event
| |
| − | |-
| |
| − | |ME-MH_PAROUT||O-IOMEM_EFGH-S||DRAM Command and Address Parity
| |
| − | |-
| |
| − | |ME-MH_RAS_L_ADD[16]||O-IOMEM_EFGH-S||DRAM Row Address Strobe or Column/Row Address 16
| |
| − | |-
| |
| − | |ME-MH_RESET_L||O-IOMEM_EFGH-S||DRAM Reset
| |
| − | |-
| |
| − | |ME-MH_WE_L_ADD[14]||O-IOMEM_EFGH-S||DRAM Write Enable or Column/Row Address 14
| |
| − | |-
| |
| − | |ME-MH_ZVSS||A||DRAM Interface Drive-Strength Auto-Compensation Resistor to VSS
| |
| − | |-
| |
| − | |ME0-MH0_CKE[1:0]<br/>ME1-MH1_CKE[1:0]||O-IOMEM_EFGH-S||DRAM Channel E-H DIMM 0-1 Clock Enable
| |
| − | |-
| |
| − | |ME0-MH0_CLK_H/L[1:0]<br/>ME1-MH1_CLK_H/L[1:0]||O-IOMEM_ABCD-D||DRAM Channel E-H DIMM 0-1 Differential Clock
| |
| − | |-
| |
| − | |ME0-MH0_CS_L[1:0]<br/>ME1-MH1_CS_L[1:0]||O-IOMEM_EFGH-S||DRAM Channel E-H DIMM 0-1 Chip Select
| |
| − | |-
| |
| − | |ME0-MH0_ODT[1:0]<br/>ME1-MH1_ODT[1:0]||O-IOMEM_EFGH-S||DRAM Channel E-H DIMM 0-1 Enable Pin for On Die Termination
| |
| − | |-
| |
| − | |FORCE_SELFREFRESH||I-IO18S5-S||NVDIMM Force Self-Refresh<ref name="FSR">At a power loss event FORCE_SELFREFRESH signals the processor to flush all pending writes inside and outside of the CPU caches, but not cache contents, to memory (including S-Link attached memory) and put the DRAMs into self-refresh mode. The processor asserts NV_SAVE_L when the operation has completed (< 1 ms) and the platform can signal NVDIMMs to backup the DRAM contents to non-volatile memory. NVDIMMs are not supported on {{\\|Socket sTRX4}} and {{\\|Socket sWRX8|sWRX8}}.</ref>
| |
| − | |-
| |
| − | |NV_SAVE_L||O-IO18S5-S||NVDIMM SAVE Signal<ref name="FSR"/>
| |
| − | |-
| |
| − | |P0-P3_RXP/RXN[15:0]||I-PCIE-D||PCIe Interface P0-P3<ref name="pcie">Only the I/O interfaces P0, P2, G0, and G2 are available on Socket sTRX4. The {{abbr|xGMI}} protocol is not supported on Socket sTRX4 and sWRX8.</ref> Receive Data Differential Pairs
| |
| − | |-
| |
| − | |P0-P3_TXP/TXN[15:0]||O-PCIE-D||PCIe Transmit Data Differential Pairs
| |
| − | |-
| |
| − | |P0A/P1A/P2B/P3B_ZVSS||A||PCIe Drive-Strength Auto-Compensation Resistor to VSS for P0-P3
| |
| − | |-
| |
| − | |G0-G3_RXP/RXN[15:0]||I-XGMI-D or I-PCIE-D||{{abbr|xGMI}} or PCIe Interface G0-G3<ref name="pcie"/> Receive Data Differential Pairs
| |
| − | |-
| |
| − | |G0-G3_TXP/TXN[15:0]||O-XGMI-D or O-PCIE-D||xGMI or PCIe Transmit Data Differential Pairs
| |
| − | |-
| |
| − | |G0B/G1B/G2A/G3A_ZVSS||A||PCIe Drive-Strength Auto-Compensation Resistor to VSS for G0-G3
| |
| − | |-
| |
| − | |PCIE_RST(0-3)_L||O-IO33S5-S||Reset signal for PCIe devices.<ref>The PCIE_RST1/RST3_L signals are not available on Socket sTRX4.</ref> Type-0: from die 0-3, Type-1/2: from I/O die
| |
| − | |-
| |
| − | |WAFL_RXP/RXN[1:0]||I-WAFL-D||{{abbr|WAFL}}<ref>The {{abbr|WAFL}} interface is not available on Socket sTRX4 and sWRX8.</ref> Receive Data Differential Pairs
| |
| − | |-
| |
| − | |WAFL_TXP/TXN[1:0]||O-WAFL-D||WAFL Transmit Data Differential Pairs
| |
| − | |-
| |
| − | |WAFL(0-3)_ZVSS||A||WAFL Drive-Strength Auto-Compensation Resistor to VSS; Type-0: die 0-3, Type-1/2: I/O die
| |
| − | |-
| |
| − | |SATA(0-3)(0-7)_RXP/RXN||I-SATA-D||SATA Receive Data Differential Pairs (alt. func. of P0, P1, G2, and G3<ref name="pcie"/> lane 0-7)
| |
| − | |-
| |
| − | |SATA(0-3)(0-7)_TXP/TXN||O-SATA-D||SATA Transmit Data Differential Pairs
| |
| − | |-
| |
| − | |DEVSLP(0-1)||I-IO33S5-OD||SATA {{abbr|DEVSLP}}
| |
| − | |-
| |
| − | |SGPIO(0-3)_CLK||O-IO33S5-S||{{abbr|SGPIO}} Interface 0-3<ref>The SGPIO interfaces 1 and 3 are not available on Socket sTRX4.</ref> CLK Output; Type-0: from die 0-3, Type-1/2: from I/O die
| |
| − | |-
| |
| − | |SGPIO(0-3)_DATAIN||I-IO33S5-S||Type-0: SGPIO DATA Input, Type-1/2: Reserved
| |
| − | |-
| |
| − | |SGPIO(0-3)_DATAOUT||O-IO33S5-S||SGPIO DATA Output
| |
| − | |-
| |
| − | |SGPIO(0-3)_LOAD||O-IO33S5-S||SGPIO LOAD Output
| |
| − | |-
| |
| − | |XGBE(0-3)(0-3)_RXP/RXN||||XGBE Receive Data Differential Pairs (alt. func. of P0, P1, G2, G3 lane 4-7)<ref name="noxgbe">XGBE is not supported on Socket SP3, sTRX4, and sWRX8.</ref>
| |
| − | |-
| |
| − | |XGBE(0-3)(0-3)_TXP/TXN||||XGBE Transmit Data Differential Pairs
| |
| − | |-
| |
| − | |MDIO(0-7)_SCL||||{{abbr|MDIO}} Port 0-7 Clock (alt. func. of SGPIO interface)
| |
| − | |-
| |
| − | |MDIO(0-7)_SDA||||MDIO Data
| |
| − | |-
| |
| − | |USB_0/1_HSD(0-3)P/N||B-IO33S5-D||USB Port 0-3 High Speed I/O Differential Pairs; Type-0: from die 0/1 (die 0 ports 0-1, die 1 ports 2-3), Type-1/2: from I/O die
| |
| − | |-
| |
| − | |USB_0/1_SS_(0-3)RXP/RXN||I-USB_S5-D||USB Port 0-3 Super Speed Receive Differential Pairs; Type-0: from die 0/1 (die 0 ports 0-1, die 1 ports 2-3), Type-1/2: from I/O die
| |
| − | |-
| |
| − | |USB_0/1_SS_(0-3)TXP/TXN||O-USB_S5-D||USB Port 0-3 Super Speed Transmit Differential Pairs
| |
| − | |-
| |
| − | |USB_OC(0-3)_L||I-IO33S5-S||USB Port 0-3 Over Current signal from USB connector; Type-0: to die 0, 0, 1, 1; Type-1/2: to I/O die
| |
| − | |-
| |
| − | |USB(0-3)_0/1_ZVSS||A||USB Port 0-3 Drive-Strength Auto-Compensation Resistor to VSS; Type-0: die 0/1, Type-1/2: I/O die
| |
| − | |-
| |
| − | |UART(0-1)_CTS_L||I-IO33-S||{{abbr|UART}} Clear To Send Input (alt. func. of UART(2-3)_RXD)
| |
| − | |-
| |
| − | |UART(0-1)_INTR||I-IO33-S||UART Interrupt Request
| |
| − | |-
| |
| − | |UART(0-1)_RTS_L||O-IO33-S||UART Request To Send Output (alt. func. of UART(2-3)_TXD)
| |
| − | |-
| |
| − | |UART(0-3)_RXD||I-IO33-S||UART Receive Data
| |
| − | |-
| |
| − | |UART(0-3)_TXD||O-IO33-S||UART Transmit Data
| |
| − | |-
| |
| − | |SPI_CLK||O-IO18-S||{{abbr|SPI}} Clock
| |
| − | |-
| |
| − | |SPI_DO||B-IO18-S||SPI Data Out or Data[0] for multi-I/O SPI/eSPI device
| |
| − | |-
| |
| − | |SPI_DI||B-IO18-S||SPI Data In or Data[1]
| |
| − | |-
| |
| − | |SPI_WP_L||B-IO18-S||SPI Write Protect or Data[2]
| |
| − | |-
| |
| − | |SPI_HOLD_L||B-IO18-S||SPI Hold Signal (asserted low to hold the SPI transaction) or Data[3]
| |
| − | |-
| |
| − | |PSP_ROM_CS_L<br/>SPI_TPM_CS_L||O-IO18-S||SPI Chip Select for {{abbr|PSP}} ROM or {{abbr|TPM}}
| |
| − | |-
| |
| − | |SPI_CS1/CS2_L||O-IO18-S||SPI Chip Select
| |
| − | |-
| |
| − | |ESPI_CLK||O-IO18-S||{{abbr|ESPI}} Clock (alt. func. of SPI_CLK)
| |
| − | |-
| |
| − | |ESPI_DAT(0-3)||B-IO33-S||ESPI Data[0], Data[1:0], Data[3:0] (alt. func. of SPI_DO/DI/WP_L/HOLD_L)
| |
| − | |-
| |
| − | |ESPI_CS_L||O-IO18-S||ESPI Chip Select (SPI_CS2_L)
| |
| − | |-
| |
| − | |ESPI_ALERT_L||I-IO18-S||ESPI Alert Input (LDRQ0_L); Requests service from eSPI master
| |
| − | |-
| |
| − | |ESPI_RESET_L||I-IO33-S||ESPI Reset Input (KBRST_L); PCIE_RST0_L suggested as reset output
| |
| − | |-
| |
| − | |LPC||ROM,||1=SPI ROM (default)
| |
| − | |-
| |
| − | |LAD(0-3)||B-IO33-S||{{abbr|LPC}} Command/Address/Data
| |
| − | |-
| |
| − | |LDRQ0_L||I-IO33-S||Encoded DMA/Bus Master Request 0
| |
| − | |-
| |
| − | |LFRAME_L||O-IO33-S||LPC Bus Frame
| |
| − | |-
| |
| − | |LPCCLK(0-1)||O-IO33-S||LPC 33 MHz Clock
| |
| − | |-
| |
| − | |LPC_CLKRUN_L||B-IO33-OD||LPC Clock Run Signal
| |
| − | |-
| |
| − | |LPC_PD_L||O-IO33S5-S||LPC Power Down
| |
| − | |-
| |
| − | |LPC_PME_L||I-IO33S5-S||LPC Power Management Event
| |
| − | |-
| |
| − | |LPC_RST_L||O-IO33S5-S||LPC Reset
| |
| − | |-
| |
| − | |LPC_SMI_L||I-IO33-S||LPC System Management Interrupt
| |
| − | |-
| |
| − | |SERIRQ||B-IO33-S||Serial IRQ for DMA
| |
| − | |-
| |
| − | |EMMC_CLK||||{{abbr|eMMC}} Clock Output (0-200 MHz)
| |
| − | |-
| |
| − | |EMMC_CMD||||eMMC Command/Response (LPC_PD_L)
| |
| − | |-
| |
| − | |EMMC_DAT(0-7)||||eMMC Data (alt. func. of LAD0-LAD3, LPCCLK0, LPC_CLKRUN_L, LPCCLK1, SERIRQ)
| |
| − | |-
| |
| − | |EMMC_DS||||eMMC HS400 Data Strobe Input (LFRAME_L)
| |
| − | |-
| |
| − | |EMMC_PWR_CTRL||||(LPC_PME_L)
| |
| − | |-
| |
| − | |I2C(0-5)_SCL||B-DUAL-OD||{{abbr|I<sup>2</sup>C}} Port 0-5 Clock
| |
| − | |-
| |
| − | |I2C(0-5)_SDA||B-DUAL-OD||I<sup>2</sup>C Data
| |
| − | |-
| |
| − | |SCL0||B-IO33-OD||{{abbr|SMBus}} Port 0 Clock (alt. func. of I2C2)
| |
| − | |-
| |
| − | |SDA0||B-IO33-OD||SMBus Port 0 Data
| |
| − | |-
| |
| − | |SCL1||B-IO33S5-OD||SMBus Port 1 Clock (alt. func. of I2C3)
| |
| − | |-
| |
| − | |SDA1||B-IO33S5-OD||SMBus Port 1 Data
| |
| − | |-
| |
| − | |HP_SCL, HP_SDA||||Hotplug SMBus (I2C0)
| |
| − | |-
| |
| − | |SFP_SCL, SFP_SDA||||{{abbr|SFP}} Bus (I2C1)
| |
| − | |-
| |
| − | |SPD_SCL, SPD_SDA||||{{abbr|SPD}} Bus (I2C2)
| |
| − | |-
| |
| − | |BMC_SCL, BMC_SDA||||{{abbr|BMC}} SMBus (I2C3)
| |
| − | |-
| |
| − | |AGPIO*_(0-3)||||Advanced {{abbr|GPIO}} pin for interrupt, wake, or I/O; Type-0: die 0-3, Type-1/2: I/O die
| |
| − | |-
| |
| − | |EGPIO*_(0-3)||||Enhanced GPIO for I/O only; Type-0: die 0-3, Type-1/2: I/O die
| |
| − | |-
| |
| − | |EGPIO*||||Enhanced GPIO for I/O only; Type-0: die 0, Type-1/2: I/O die
| |
| − | |-
| |
| − | |REFCLK100SSC_P/N||O-CLK-D or I-CLK-D||100 MHz CPU Reference Clock; Output from {{abbr|BSP}}, or input for {{abbr|BSP:AP}}; {{abbr|SSC}} option
| |
| − | |-
| |
| − | |GPP_CLK(0-3)BP/N||O-CLK-D||100 MHz Differential PCIe Reference Clock; Type-0: from die 0-3, Type-1/2: from I/O die
| |
| − | |-
| |
| − | |GPP_CLK(0-3)TP/N||O-CLK-D||100 MHz Differential PCIe Reference Clock; Type-0: from die 0-3, Type-1/2: from I/O die
| |
| − | |-
| |
| − | |X156M_H/L[3:0]||I-XGBECLK-D||Differential 156.25 MHz Reference CLK Input<ref name="noxgbe"/>; Type-0: to die 0-3, Type-1/2: to I/O die
| |
| − | |-
| |
| − | |X32K_X1/X2||I-IO18S5-S||32768 Hz Clock XTAL or (X32K_X1 only) Clock Input, for the integrated {{abbr|RTC}}
| |
| − | |-
| |
| − | |X48M_X1/X2||I-IO18S5-S||48 MHz Clock XTAL or (X48M_X1 only) Clock Input, for the integrated clock generator
| |
| − | |-
| |
| − | |RTCCLK||O-IO18S5-S||32 kHz Real Time Clock Output, e.g. BSP to AP, or for a device requiring an RTC clock
| |
| − | |-
| |
| − | |KBRST_L||I-IO33-S||Keyboard Controller Reset Input (warm reset)
| |
| − | |-
| |
| − | |PM_INTR_L||I-IO33-S||PM_INTR_L function for NVMe drive I<sup>2</sup>C subsystem and PCIe hot-plug subsystem
| |
| − | |-
| |
| − | |PWR_BTN_L||I-IO33S5||Power Button; Requests sleep state or causes wake event
| |
| − | |-
| |
| − | |PWR_GOOD||I-IO33S5-S||Power Good Input; Asserted when all voltages and clock inputs are within specification; From motherboard to {{abbr|BSP}}, or from BSP to {{abbr|BSP:AP}}
| |
| − | |-
| |
| − | |PWRGD_OUT||O-IO33S5-S||Power Good Output, from BSP to PWR_GOOD input of AP
| |
| − | |-
| |
| − | |PWROK||B-IO18-OD||Power OK; Asserted by the processor after all power planes are active, the system clock generators are powered up and run stably
| |
| − | |-
| |
| − | |RESET_L||B-IO18-OD||Bidirectional signal that resets the processor when asserted; Normally controlled by an internal state machine but can also be asserted by a second external source
| |
| − | |-
| |
| − | |RSMRST_L||I-IO18S5-S||Resume Reset from motherboard, resets all in-processor S5 and S0 logic; Asserted on power up, deasserted when S5 power supplies are within specification
| |
| − | |-
| |
| − | |SLP_S3/S5_L||O-IO33S5-S||S3/S5 Sleep State Power Plane Control Signals<br/><table class="wikitable"><tr><th>SLP_S3_L</th><th>SLP_S5_L</th><th>State</th></tr><tr><td>High</td><td>High</td><td>S0</td></tr><tr><td>Low</td><td>High</td><td>S3</td></tr><tr><td>Low</td><td>Low</td><td>S4/S5</td></tr></table>
| |
| − | |-
| |
| − | |SYS_RESET_L||I-IO33S5-S||System Reset Input (reset button)
| |
| − | |-
| |
| − | |WAKE_L||B-IO33S5-S||PCIe WAKE_L signal, wake system out of sleep state
| |
| − | |-
| |
| − | |WOL(0-3)||I_IO33S5-OD||Wake-on-LAN function
| |
| − | |-
| |
| − | |NMI_SYNC_FLOOD_L||I-IO33-S||This pin signals a {{abbr|NMI}} or Sync Flood<ref>In the [[HyperTransport]] protocol Sync packets request serial link resynchronization. Sync Flood is a line state receivers recognize as unrecoverable and as signal to stop propagating potentially bad data. In other words this historic term refers to a low-level fatal error signal. The condition is passed on through the Data Fabric and ultimately requires a system reset.</ref>
| |
| − | |-
| |
| − | |ALERT_L||O-IO33-OD||Programmable pin that can indicate different events, including a {{abbr|SB-TSI}} interrupt
| |
| − | |-
| |
| − | |PROCHOT_L||I-IO33-OD||Asserted to force the processor into {{abbr|HTC}}-active state
| |
| − | |-
| |
| − | |SIC||I-DUAL-OD||Sideband Interface Clock<ref>The Sideband Interface (SBI) a.k.a. {{abbr|APML}} is a {{abbr|SMBus}} interconnect to the processor's {{abbr|SB-RMI}} and {{abbr|SB-TSI}} interfaces.</ref>
| |
| − | |-
| |
| − | |SID||B-DUAL-OD||Sideband Interface Data
| |
| − | |-
| |
| − | |THERMTRIP_L||B-IO33-OD||{{x86|Thermal protection|Temperature Trip}} Input/Output
| |
| − | |-
| |
| − | |BP(0-5)||B-IO18-S||Break Point Indicator; Used to trigger external test equipment such as oscilloscopes and logic analyzers
| |
| − | |-
| |
| − | |DBREQ_L||I-IO18S5-S||Debug Request input to JTAG controller
| |
| − | |-
| |
| − | |TCK||I-IO18S5-S||{{abbr|JTAG}} Clock
| |
| − | |-
| |
| − | |TDI||I-IO18S5-S||JTAG Data Input
| |
| − | |-
| |
| − | |TDO||O-IO18S5-S||JTAG Data Output
| |
| − | |-
| |
| − | |TMS||I-IO18S5-S||JTAG Mode Select
| |
| − | |-
| |
| − | |TRST_L||I-IO18S5-S||JTAG Reset
| |
| − | |-
| |
| − | |TEST*||||Test Pins
| |
| − | |-
| |
| − | |XTRIG_L[7:4]||B-IO18-OD||XTRIG Debug Signals
| |
| − | |-
| |
| − | |SVC_CPU, SVC_SOC||O-IO18-S||Serial VID Interface Clock for VDDCR_CPU, VDDCR_SOC regulator
| |
| − | |-
| |
| − | |SVD_CPU, SVD_SOC||B-IO18-S||Serial VID Interface Data
| |
| − | |-
| |
| − | |SVT_CPU, SVT_SOC||I-IO18-S||Serial VID Interface Telemetry
| |
| − | |-
| |
| − | |VDDBT_RTC_G||S||Integrated Real Time Clock battery power supply, 1.5 V ±5% or 1.8 V ±5%<ref>From 1.5 V or 1.8 V always on supply, or 3 V coin cell battery using an {{abbr|LDO}}, or jumpered to VSS to "Clear CMOS".</ref>
| |
| − | |-
| |
| − | |VDDCR_CPU||S||Supply voltage for the CPU core
| |
| − | |-
| |
| − | |VDDCR_CPU_SENSE||A||VDDCR_CPU voltage sense output, differential feedback with VSS_SENSE_A
| |
| − | |-
| |
| − | |VDDCR_SOC||S||Supply voltage for the Northbridge (integrated {{abbr|FCH}}, Ethernet, SATA, {{abbr|NBIO}}, {{abbr|SMU}}, DDR PHY logic)
| |
| − | |-
| |
| − | |VDDCR_SOC_SENSE||A||VDDCR_SOC voltage sense output, differential feedback with VSS_SENSE_B
| |
| − | |-
| |
| − | |VDDCR_SOC_S5||S||Always on 0.9 V ± 20 mV supply voltage for the FCH and USB PHYs
| |
| − | |-
| |
| − | |VDDCR_SOC_S5_SENSE||A||VDDCR_SOC_S5 voltage sense output, differential feedback with VSS_SENSE_B
| |
| − | |-
| |
| − | |VDDIO_MEM_S3_ABCD/EFGH||S||1.2 V (1.14 - 1.28 V) supply voltage for the DRAM PHYs, channels A-D / E-H
| |
| − | |-
| |
| − | |VDDIO_MEM_S3_ABCD_FB_H/L||A||VDDIO_MEM_S3_ABCD voltage differential feedback to VDDIO_MEM_S3_ABCD regulator
| |
| − | |-
| |
| − | |VDDIO_MEM_S3_EFGH_FB_H/L||A||VDDIO_MEM_S3_EFGH voltage differential feedback
| |
| − | |-
| |
| − | |VDD_18||S||1.8 V ±5% supply voltage for analog circuits
| |
| − | |-
| |
| − | |VDD_18_SENSE||A||VDD_18 voltage sense output, differential feedback with VSS_SENSE_A
| |
| − | |-
| |
| − | |VDD_18_S5||S||Always on 1.8 V ±5% supply voltage for analog circuits
| |
| − | |-
| |
| − | |VDD_18_S5_SENSE||A||VDD_18_S5 voltage sense output, differential feedback with VSS_SENSE_A
| |
| − | |-
| |
| − | |VDD_33||S||3.3 V ±5% supply voltage for GPIO
| |
| − | |-
| |
| − | |VDD_33_SENSE||A||VDD_33 voltage sense output, differential feedback with VSS_SENSE_B
| |
| − | |-
| |
| − | |VDD_33_S5||S||Always on 3.3 V ±5% supply voltage for GPIO
| |
| − | |-
| |
| − | |VDD_33_S5_SENSE||A||VDD_33_S5 voltage sense output, differential feedback with VSS_SENSE_B
| |
| − | |-
| |
| − | |VSS||S||Ground
| |
| − | |-
| |
| − | |VSS_SENSE_A||A||VSS sense output for VDDCR_CPU, VDD_18, VDD_18_S5 regulator
| |
| − | |-
| |
| − | |VSS_SENSE_B||A||VSS sense output for VDDCR_SOC, VDD_33, VDD_33_S5, VDDCR_SOC_S5 regulator
| |
| − | |-
| |
| − | |{{vanchor|CORETYPE}}||||Processor Core Type Indicator; NC = Not connected, VSS = connected to VSS on the package<br/><table class="wikitable"><tr><th>Processor</th><th>CORETYPE</th></tr><tr><td>SP3 Type-0</td><td>VSS</td></tr><tr><td>SP3 Type-1/2</td><td>NC</td></tr><tr><td>{{\\|Socket TR4|TR4}}/{{\\|Socket sTRX4|sTRX4}}/{{\\|Socket sWRX8|sWRX8}}</td><td>NC</td></tr></table><!--AMD-55414-1.10 Sec 11.5.2; AMD-55809-1.03 Tbl 35; AMD-56724-1.00 Tbl 42 & Sec 9.5; AMD-56437-1.01 Tbl 49-->
| |
| − | |-
| |
| − | |{{vanchor|SP3R1}}, {{vanchor|SP3R2}}||||Processor Family Revision Identifier (electrical keying); NC = Not connected, VSS = connected to VSS on the package<br/><table class="wikitable"><tr><th>Processor</th><th>SP3R1</th><th>SP3R2</th></tr><tr><td>SP3</td><td>NC</td><td>VSS</td></tr><tr><td>TR4</td><td>NC</td><td>NC</td></tr><tr><td>sTRX4</td><td>VSS</td><td>NC</td></tr><tr><td>sWRX8</td><td>NC</td><td>VSS</td></tr></table><!--AMD-55414-1.10 Sec 11.5.3; AMD-55809-1.03 Tbl 35 & Sec 11.4; AMD-56724-1.00 Tbl 42; AMD-56437-1.01 Tbl 49-->
| |
| − | |-
| |
| − | |CPU_PRESENT_L||||CPU Presence Indicator, connected to VSS on the package
| |
| − | |-
| |
| − | |SA[2:0]||I-IO18S5-S||Socket Identifier; 0 = connected to VSS, 1 = 10 kΩ PU to VDD_18_S5<br/><table class="wikitable"><tr><th>Socket</th><th>SA[2]</th><th>SA[1]</th><th>SA[0]</th></tr><tr><td>SP3 {{abbr|BSP}}</td><td>0</td><td>0</td><td>0</td></tr><tr><td>SP3 {{abbr|BSP:AP}} (2P systems)</td><td>0</td><td>0</td><td>1</td></tr><tr><td>sTRX4/sWRX8</td><td>0</td><td>0</td><td>0</td></tr></table><!--AMD-55414-1.10 Tbl 81; AMD-56515-0.81 Tbl 35; AMD-56724-1.00 Tbl 42; AMD-56437-1.01 Tbl 49-->
| |
| − | |-
| |
| − | |RSVD||||Reserved
| |
| − | |}
| |
| − |
| |
| − | <references/>
| |
| − |
| |
| − | ==== Pin Types ====
| |
| − | {| class="wikitable"
| |
| − | !colspan="2"|Voltage Domain Internal to {{abbr|SoC}}, derived from VDDIO_MEM_S3_*
| |
| − | |-
| |
| − | |I/O-xGMI/PCIE/SATA/WAFL-D||Input / Output, {{abbr|xGMI}} / PCIe / SATA / {{abbr|WAFL}} Domain, Differential
| |
| − | |-
| |
| − | !colspan="2"|VDDCR_SOC_S5 Voltage Domain
| |
| − | |-
| |
| − | |I/O/B-USB_S5-D||Input / Output / Bidirectional, USB, Differential
| |
| − | |-
| |
| − | |I/O-CLK-D||Input / Output, CLK, Differential
| |
| − | |-
| |
| − | !colspan="2"|Other Voltage Domains
| |
| − | |-
| |
| − | |I/O/B-IOMEM_ABCD-D/S||Input / Output / Bidirectional, VDDIO_MEM_S3_ABCD Voltage Domain, Differential / Single-Ended
| |
| − | |-
| |
| − | |I/O/B-IOMEM_EFGH-D/S||Input / Output / Bidirectional, VDDIO_MEM_S3_EFGH, Differential / Single-Ended
| |
| − | |-
| |
| − | |I/O/B-IO18-D/S/OD||Input / Output / Bidirectional, VDD_18, Differential / Single-Ended / Open Drain
| |
| − | |-
| |
| − | |I/O/B-IO18S-D/S/OD||Input / Output / Bidirectional, VDD_18_S5, Differential / Single-Ended / Open Drain
| |
| − | |-
| |
| − | |I/O/B-IO33-D/S/OD||Input / Output / Bidirectional, VDD_33, Differential / Single-Ended / Open Drain
| |
| − | |-
| |
| − | |I/O/B-IO33S5-D/S/OD||Input / Output / Bidirectional, VDD_33_S5, Differential / Single-Ended / Open Drain
| |
| − | |-
| |
| − | |I/B-DUAL-OD||Input / Bidirectional, VDD_18 or VDD_33, Open Drain
| |
| − | |-
| |
| − | |A||Analog
| |
| − | |-
| |
| − | |S||Supply Voltage
| |
| − | |}
| |
| | | | |
| | == Bibliography == | | == Bibliography == |
| | * David. S. (March 2018). "[https://fuse.wikichip.org/news/1064/isscc-2018-amds-zeppelin-multi-chip-routing-and-packaging/ ISSCC 2018: AMD’s Zeppelin; Multi-chip routing and packaging]" | | * David. S. (March 2018). "[https://fuse.wikichip.org/news/1064/isscc-2018-amds-zeppelin-multi-chip-routing-and-packaging/ ISSCC 2018: AMD’s Zeppelin; Multi-chip routing and packaging]" |
| − | * {{cite techdoc|title=Socket SP3 Design Specification|publ=AMD|pid=55260|rev=1.16|date=2020-08}} | + | * AMD (November 2017). "Thermal Design Guide for Socket SP3 Processors" |
| − | * {{cite techdoc|title=Thermal Design Guide for SP3 Processors|url=https://www.amd.com/system/files/TechDocs/55423.pdf|publ=AMD|pid=55423|rev=3.00|date=2017-11-13}}
| |
| − | * {{cite techdoc|title=Socket SP3 Processor Functional Data Sheet for AMD Family 17h Models 00h–0Fh, Family 17h Models 30h–3Fh, and Family 19h Models 00h–0Fh|publ=AMD|pid=55426|rev=1.04|date=2020-10}}
| |
| − | * {{cite techdoc|title=Functional Data Sheet for sTRX4 and sWRX8 Processors|publ=AMD|pid=56515|rev=0.81|date=2019-08}}
| |
| − | * {{cite techdoc|title=Electrical Data Sheet for AMD Family 17h Models 00h–0Fh and 30h–3Fh and Family 19h Models 00h–0Fh Socket SP3 Processors|publ=AMD|pid=55441|rev=0.65|date=2020-07}}
| |
| − | * {{cite techdoc|title=Electrical Data Sheet for AMD Family 17h Models 30h–3Fh and Family 19h Model 08h sTRX4, sWRX8 Processors|publ=AMD|pid=55441cpw|rev=0.66|date=2021-03}}
| |
| − | * {{cite techdoc|title=Infrastructure Roadmap (IRM) for Socket SP3 Processors|publ=AMD|pid=55418|rev=1.18|date=2020-10}}
| |
| − | * {{cite techdoc|title=Infrastructure Roadmap for sTRX4 and sWRX8 Processors|publ=AMD|pid=56443|rev=0.92|date=2021-07}}
| |
| − | * {{cite techdoc|title=Socket SP3 Processor Motherboard Design Guide for AMD Family 17h Models 00h-0Fh, Models 30h-3Fh, and Family 19h Models 00h-0Fh|publ=AMD|pid=55414|rev=1.10|date=2020-11}}
| |
| − | * {{cite techdoc|title=SP3r2 Processor Motherboard Design Guide|publ=AMD|pid=55809|rev=1.03|date=2017-10}}
| |
| − | * {{cite techdoc|title=Motherboard Design Guide for sTRX4 High-End Desktop Processors|publ=AMD|pid=56724|rev=1.00|date=2020-09}}
| |
| − | * {{cite techdoc|title=Motherboard Design Guide for sTRX4 and sWRX8 Processors|publ=AMD|pid=56437|rev=1.01|date=2021-06}}
| |
| − | * {{cite techdoc|title=Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors|publ=AMD|pid=54945|rev=3.00|date=2019-04-14}}
| |
| − | * {{cite techdoc|title=Preliminary Processor Programming Reference (PPR) for AMD Family 17h Model 31h, Revision B0 Processors|publ=AMD|pid=55803|rev=0.93|date=2020-10-28}}
| |
| − | * {{cite techdoc|title=NVDIMM-N Support for Family 17h Models 00h-0Fh Processors Application Note|publ=AMD|pid=56014|rev=0.74|date=2018-05}}
| |
| − | * {{cite techdoc|title=NVDIMM-N Support for Socket SP3 Family 17h Models 30h–3Fh Processors Application Note|publ=AMD|pid=56333|rev=0.60|date=2020-04}}
| |
| − | * {{cite techdoc|title=Revision Guide for AMD Family 17h Models 00h-0Fh Processors|publ=AMD|pid=55449|rev=1.19|date=2019-12}}
| |
| − | * {{cite techdoc|title=Revision Guide for AMD Family 17h Models 30h-3Fh Processors|publ=AMD|pid=56323|rev=0.78|date=2021-02}}
| |
| − | * {{cite techdoc|title=Revision Guide for AMD Family 19h Models 00h-0Fh Processors|publ=AMD|pid=56683|rev=1.04|date=2021-06}}
| |
| − | * {{cite article|authors=Beck, Noah;White, Sean;Paraschou, Milam;Naffziger, Samuel|title=‘Zeppelin’: An SoC for multichip architectures|date=2018-02-11|conference=Proceedings of IEEE ISSCC 2018|pages=40-42|doi=10.1109/ISSCC.2018.8310173}}
| |
| − | * {{cite article|authors=Burd, Thomas;Beck, Noah;White, Sean;Paraschou, Milam;Kalyanasundharam, Nathan;Donley, Gregg;Smith, Alan;Hewitt, Larry;Naffziger, Samuel|title=“Zeppelin”: An SoC for Multichip Architectures|date=2018-10-26|journal=IEEE JSSC|volume=54|issue=1|pages=133-143|doi=10.1109/JSSC.2018.2873584}}
| |
| − | * {{cite article|authors=Singh, Teja;Rangarajan, Sundar;John, Deepesh;Schreiber, Russell;Oliver, Spence;Seahra, Rajit;Schaefer, Alex|title=Zen 2: The AMD 7nm Energy-Efficient High-Performance x86-64 Microprocessor Core|date=2020-02|conference=Proceedings of IEEE ISSCC 2020|pages=42-44|doi=10.1109/ISSCC19947.2020.9063113}}
| |
| − | * {{cite article|authors=Naffziger, Samuel;Lepak, Kevin;Paraschou, Milam;Subramony, Mahesh|title=AMD Chiplet Architecture for High-Performance Server and Desktop Products|date=2020-02|conference=Proceedings of IEEE ISSCC 2020|pages=44-45|doi=10.1109/ISSCC19947.2020.9063103}}
| |
| − | * {{cite techdoc|authors=Naffziger, Samuel|title=AMD Chiplet Architecture for High-Performance Server and Desktop Products|url=https://www.slideshare.net/AMD/amd-chiplet-architecture-for-highperformance-server-and-desktop-products|publ=IEEE ISSCC 2020|date=2020-02-17}}
| |
| − | * "EPYC Tech Day", June 20, 2017
| |
| − | * 2nd Gen AMD EPYC launch event, August 7, 2019
| |
| − | | |
| − | == See also ==
| |
| − | * {{\\|Socket AM4}}
| |
| − | * {{\\|Socket TR4}}
| |
| − | * {{\\|Socket sTRX4}}
| |
| − | * {{\\|Socket sWRX8}}
| |
| − | * {{\\|Socket SP5}}
| |
| − | | |
| − | [[Category:amd]]
| |
