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| |manufacturer 2=GlobalFoundries | | |manufacturer 2=GlobalFoundries |
| |introduction=October 8, 2020 | | |introduction=October 8, 2020 |
− | |process=7nm, 12nm | + | |process=7nm |
| |cores=64 | | |cores=64 |
− | |cores 2=56 | + | |cores 2=48 |
− | |cores 3=48 | + | |cores 3=32 |
− | |cores 4=32 | + | |cores 4=16 |
− | |cores 5=28 | + | |cores 5=12 |
− | |cores 6=24 | + | |cores 6=8 |
− | |cores 7=16 | + | |cores 7=6 |
− | |cores 8=12
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− | |cores 9=8
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− | |cores 10=6
| |
| |type=Superscalar | | |type=Superscalar |
| |oooe=Yes | | |oooe=Yes |
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| |extension 27=UMIP | | |extension 27=UMIP |
| |extension 28=CLZERO | | |extension 28=CLZERO |
− | |extension 29=VAES
| |
− | |extension 30=VPCLMUL
| |
| |predecessor=Zen 2 | | |predecessor=Zen 2 |
| |predecessor link=amd/microarchitectures/zen 2 | | |predecessor link=amd/microarchitectures/zen 2 |
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| | | |
| == Codenames == | | == Codenames == |
− | [[File:amd zen2-3 roadmap.png|thumb|right|Zen 3 on the roadmap]] | + | [[File:amd zen2-3 roadmap.png|400px|right]] |
| + | {{future information}} |
| | | |
− | '''Product Codenames:'''
| |
| {| class="wikitable" | | {| class="wikitable" |
| |- | | |- |
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| | {{amd|Milan|l=core}} || Up to 64/128 || High-end server [[multiprocessors]] | | | {{amd|Milan|l=core}} || Up to 64/128 || High-end server [[multiprocessors]] |
| |- | | |- |
− | | {{amd|Chagall|l=core}} || Up to 64/128 || Workstation & enthusiasts market processors | + | | {{amd|Genesis Peak|l=core}} || ?/? || Workstation & enthusiasts market processors |
| |- | | |- |
| | {{amd|Vermeer|l=core}} || Up to 16/32 || Mainstream to high-end desktops & enthusiasts market processors | | | {{amd|Vermeer|l=core}} || Up to 16/32 || Mainstream to high-end desktops & enthusiasts market processors |
| |- | | |- |
− | | {{amd|Cezanne|l=core}} || Up to 8/16 || Mainstream APUs with GPUs | + | | {{amd|Cezanne|l=core}} || Up to 8/16 || Mainstream desktop & mobile processors with GPU |
− | |}
| |
− | | |
− | '''Architectural Codenames:'''
| |
− | {| class="wikitable"
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− | |-
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− | ! Arch !! Codename
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− | |-
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− | | Core || Cerebrus
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− | |-
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− | | CCD || Breckenridge
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− | |}
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− | | |
− | == Products ==
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− | {{future information}}
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− | | |
− | {| class="wikitable"
| |
− | |-
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− | ! Processor Series !! Cores/Threads !! Market
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− | |-
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− | | EPYC 7003 "{{amd|Milan|l=core}}" || Up to 64/128 || High-end server [[multiprocessors]]
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− | |-
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− | | {{amd|Trento|l=core}}<!--s/a Milan page--> || ?/? || High-performance computing
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− | |-
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− | | Ryzen Threadripper 5900 "{{amd|Chagall|l=core}}" || Up to 64/128 || Workstation processors
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− | |-
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− | | Ryzen 5000 "{{amd|Vermeer|l=core}}" || Up to 16/32 || Mainstream to high-end desktops & enthusiasts market processors
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− | |-
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− | | Ryzen 5000 APU "{{amd|Cezanne|l=core}}" || Up to 8/16 || Mainstream desktop & mobile processors with integrated GPU
| |
| |} | | |} |
| | | |
| == Process technology == | | == Process technology == |
− | Zen 3 is fabricated on [[TSMC]]'s [[7 nm process|7nm+ process]] for the Core Compute Die (CCD), the same process used in Zen 2 Refresh processors, as well as [[GlobalFoundries]] [[14 nm process|12nm process]] for the Input/Output Die (IOD). | + | Zen 3 will be fabricated on [[TSMC]]'s [[7 nm process|7nm+ process]], the same process used in Zen 2 Refresh processors. |
| | | |
− | Note: Only the APU series of microprocessors retains the monolithic design, so they are fabricated solely on [[TSMC]]'s [[7 nm process|7nm+ process]].
| + | == Architecture == |
− | | |
− | == Compiler support == | |
− | {| class="wikitable"
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− | |-
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− | ! Compiler !! Arch-Specific || Arch-Favorable
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− | |-
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− | | [[GCC]] || <code>-march=znver3</code> || <code>-mtune=znver3</code>
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− | |-
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− | | [[LLVM]] || <code>-march=znver3</code> || <code>-mtune=znver3</code>
| |
− | |}
| |
− | * '''Note:''' Initial support in GCC 10.3 and LLVM 12.0.
| |
| | | |
− | == Architecture ==
| + | There is very limited information available about the architectural improvements of Zen 3. |
| | | |
| === Key changes from {{\\|Zen 2}} === | | === Key changes from {{\\|Zen 2}} === |
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| ** Higher [[IPC]] (AMD self-reported +19% IPC) | | ** Higher [[IPC]] (AMD self-reported +19% IPC) |
| ** Front-end | | ** Front-end |
− | *** Increased branch prediction bandwidth
| + | ** Increased branch prediction bandwidth |
| *** "zero-bubble" branch prediction | | *** "zero-bubble" branch prediction |
| *** L1 BTB doubled from 512 to 1024 entries | | *** L1 BTB doubled from 512 to 1024 entries |
− | *** Improved prefetching
| + | ** Improved prefetching |
− | *** Improved µop cache
| + | ** Improved µop cache |
− | ** Back-end
| + | * Back-end |
− | *** Floating point unit:
| + | ** Floating point unit: |
− | **** FMA latency reduced by 1 cycle from 5 to 4.
| + | *** FMA latency reduced by 1 cycle from 5 to 4. |
− | **** Fifth and sixth dedicated execution ports added for floating point store and FP-to-int transfer, no longer sharing 2nd FADD port.
| + | *** Fifth and sixth dedicated execution ports added for floating point store and FP-to-int transfer, no longer sharing 2nd FADD port. |
− | **** Unified scheduler split into 1 scheduler per FMA/FADD/transfer port set.
| + | *** Unified scheduler split into 1 scheduler per FMA/FADD/transfer port set. |
− | **** 256b VAES and VPCLMULDQ support for doubled AES and AES-GCM cryptographic throughput.
| + | *** 256b VAES and VPCLMULDQ support for doubled AES and AES-GCM cryptographic throughout. |
− | **** Hardware implementation of BMI2 PDEP/PEXT bit scatter/gather operations, compared to prior microcode emulation.
| + | *** Hardware implementation of BMI2 PDEP/PEXT bit scatter/gather operations, compared to prior microcode emulation. |
− | *** Integer unit:
| + | ** Integer unit: |
− | **** Integer physical register file increased from 180 to 192 entries
| + | *** Integer physical register file increased from 180 to 192 entries |
− | **** Issue increased from 7 (existing 4 ALU and 3 AGU) to 10 with 1 new dedicated branch execution port and 2 separated store data pathways.
| + | *** Issue increased from 7 (existing 4 ALU and 3 AGU) to 10 with 1 new dedicated branch execution port and 2 separated store data pathways. |
− | **** Schedulers shared between pairs of ALU + AGU/branch ports instead of dedicated for each.
| + | *** Schedulers shared between pairs of ALU + AGU/branch ports instead of dedicated for each. |
− | **** Instruction redundancy increased between ports for reduced bottlenecking on a wider variety of instruction streams.
| + | *** Instruction redundancy increased between ports for reduced bottlenecking on a wider variety of instruction streams. |
− | **** 8/16/32/64 bit signed integer division/modulo latency improved from 17/22/30/46 cycles to 10/12/14/20. (Unsigned operations are ~1 cycle faster for some of both old/new cases.) Throughput improves proportionately.
| + | *** 8/16/32/64 bit signed integer division/modulo latency improved from 17/22/30/46 cycles to 10/12/14/20. (Unsigned operations are ~1 cycle faster for some of both old/new cases.) Throughput improves proportionately. |
− | *** Load/store:
| + | ** Load/store: |
− | **** Load throughput increased from 2 to 3, if not 256b.
| + | *** Load throughput increased from 2 to 3, if not 256b. |
− | **** Store throughput increased from 1 to 2, if not 256b.
| + | *** Store throughput increased from 1 to 2, if not 256b. |
− | **** Store queue increase from 48 to 64 slots.
| + | *** Store queue increase from 48 to 64 slots. |
− | **** Page table walkers tripled from 2 to 6 for TLB miss handling.
| + | *** Page table walkers tripled from 2 to 6 for TLB miss handling. |
| {{expand list}} | | {{expand list}} |
− |
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− | === New Instructions ===
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− | Zen 3 introduced the following ISA enhancements:
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− |
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− | * {{x86|VAES}} - 256-bit Vector AES instructions
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− | ** <code>VAESDEC</code> - AES Decryption Round
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− | ** <code>VAESDECLAST</code> - AES Last Decryption Round
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− | ** <code>VAESENC</code> - AES Encryption Round
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− | ** <code>VAESENCLAST</code> - AES Last Encryption Round
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− | * <code>{{x86|VPCLMULQDQ}}</code> - 256-bit Vector Carry-Less Multiplication of Quadwords
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− | * {{x86|PCID}} - Process Context Identifiers
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− | ** <code>{{x86|INVPCID}}</code> - Invalidate TLB entry(s) in a specified PCID
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− | * {{x86|INVLPGB}} - Broadcast TLB flushing
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− | ** <code>INVLPGB</code> - Invalidate TLB entry(s) with broadcast to all processors
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− | ** <code>TLBSYNC</code> - Synchronize TLB invalidations
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− | * {{x86|PKU}} - Memory Protection Keys for Users
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− | ** <code>RDPKRU</code> - Read Protection Key Rights
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− | ** <code>WRPKRU</code> - Write Protection Key Rights
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− | * {{x86|CET|CET_SS}} - Control-flow Enforcement Technology / Shadow Stack
| |
− | ** <code>CLRSSBSY</code>, <code>INCSSP</code>, <code>RDSSP</code>, <code>RSTORSSP</code>, <code>SAVEPREVSSP</code>, <code>SETSSBSY</code>, <code>WRSS</code>, <code>WRUSS</code>
| |
− | * {{x86|SME|SEV-SNP}} - 3rd generation Secure Encrypted Virtualization - Secure Nested Paging
| |
− | ** <code>PSMASH</code>, <code>PVALIDATE</code>, <code>RMPADJUST</code>, <code>RMPUPDATE</code>
| |
− | * {{x86|PSFD}} - Predictive Store Forwarding Disable (Speculation Control MSR)<ref name="amd-psf"/>
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− |
| |
− | Sources: <ref name="amd-24593-apm2"/><ref name="amd-24594-apm3"/><ref name="amd-26568-apm4"/>
| |
− |
| |
− | === Memory Hierarchy ===
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− | ==== Data and Instruction Caches ====
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− | * L0 Op Cache:
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− | ** 4,096 Ops per core, 8-way set associative
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− | ** 8 Op line size
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− | ** Parity protected
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− | * L1I Cache:
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− | ** 32 KiB per core, 8-way set associative
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− | ** 64 B line size
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− | ** Parity protected
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− | * L1D Cache:
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− | ** 32 KiB per core, 8-way set associative
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− | ** 64 B line size
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− | ** Write-back policy
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− | ** 4-5 cycles latency for Int
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− | ** 7-8 cycles latency for FP
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− | ** ECC
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− | * L2 Cache:
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− | ** 512 KiB per core, 8-way set associative
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− | ** 64 B line size
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− | ** Write-back policy
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− | ** Inclusive of L1
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− | ** ≥ 12 cycles latency
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− | ** {{abbr|DEC-TED}} ECC, tag & state arrays {{abbr|SEC-DED}}<!--7 check bits for 42 tag bits; AMD-55898-0.50 Sec 3.5-->
| |
− | * L3 Cache:
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− | ** "{{amd|Milan|l=core}}" & "{{amd|Chagall|l=core}}": 32 MiB/CCX, up to 256 MiB total
| |
− | ** "{{amd|Vermeer|l=core}}": 32 MiB/CCX, up to 64 MiB total
| |
− | ** "{{amd|Cezanne|l=core}}": 16 MiB, 8 MiB usable on some SKUs
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− | ** Shared by all cores in the {{abbr|CCX}}, configurable<ref name="amd-56375-qos"/>
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− | ** 16-way set associative
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− | ** 64 B line size
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− | ** L2 [[victim cache]]
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− | ** Write-back policy
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− | ** 46 cycles average load-to-use latency
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− | ** DEC-TED ECC, tag array & shadow tags SEC-DED<!--AMD-55898-0.50 Sec 3.5-->
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− | ** QoS Monitoring and Enforcement V2.0
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− |
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− | ==== Translation Lookaside Buffers ====
| |
− | * ITLB
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− | ** 64 entry L1 TLB, fully associative, all page sizes
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− | ** 512 entry L2 TLB, 8-way set associative
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− | *** 4-Kbyte and 2-Mbyte pages
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− | ** Parity protected
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− | * DTLB
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− | ** 64 entry L1 TLB, fully associative, all page sizes
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− | ** 2,048 entry L2 TLB, 16-way set associative
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− | *** 4-Kbyte and 2-Mbyte pages, PDEs to speed up table walks
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− | ** Parity protected
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− |
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− | All caches and TLBs are competitively shared in multi-threaded mode.
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− |
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− | ==== System DRAM ====
| |
− | * EPYC 7003 "{{amd|Milan|l=core}}":
| |
− | ** 8 channels per socket, up to 16 DIMMs, max. 4 TiB
| |
− | ** Up to PC4-25600L (DDR4-3200)
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− | ** {{abbr|SR}}/{{abbr|DR}} {{abbr|RDIMM}}, {{abbr|4R}}/{{abbr|8R}} {{abbr|LRDIMM}}, {{abbr|3DS DIMM}}, {{abbr|NVDIMM-N}}
| |
− | ** ECC supported (x4, x8, x16, chipkill)<!--AMD-55898-0.50 Sec 3.7-->
| |
− | ** DRAM bus parity and write data CRC options<!--ibid-->
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− |
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− | * Ryzen Threadripper 5900 "{{amd|Chagall|l=core}}":
| |
− | ** 8 channels, up to 8 DIMMs, max. 2 TiB
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− | ** Up to PC4-25600L (DDR4-3200)
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− | ** SR/DR {{abbr|UDIMM}}, RDIMM, LRDIMM, 3DS DIMM
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− | ** ECC supported
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− |
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− | * Ryzen 5000 "{{amd|Vermeer|l=core}}":
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− | ** 2 channels, up to 4 DIMMs, max. 128 GiB
| |
− | ** Up to PC4-25600U (DDR4-3200 UDIMM), ECC supported
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− |
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− | * Ryzen 5000 APU "{{amd|Cezanne|l=core}}":
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− | ** {{amd|Socket AM4|l=pack}}:
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− | *** 2 channels, up to 4 DIMMs, max. 128 GiB
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− | *** Up to PC4-25600U (DDR4-3200 UDIMM), ECC supported ("PRO" models)
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− | ** {{amd|FP6|FP6 package|l=pack}}, DDR4 mode:
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− | *** 2 × 64-bit channels, up to 2 DIMMs, max. 64 GiB
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− | *** Up to PC4-25600U (DDR4-3200 UDIMM), ECC supported(?)
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− | ** FP6 package, LPDDR4 mode:
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− | *** 4 × 32-bit channels, max. 32 GiB
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− | *** Up to LPDDR4X-4266
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− |
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− | Sources: <ref name="amd-56375-qos"/><ref name="amd-56665-sog-19h"/><ref name="amd-55898-ppr-1901-0.35"/><ref name="amd-55898-ppr-1901-0.50"/><ref name="amd-56178-mdg-fp6"/>
| |
| | | |
| == All Zen 3 Chips == | | == All Zen 3 Chips == |
| | | |
− | <!-- NOTE: | + | <!-- NOTE: |
| This table is generated automatically from the data in the actual articles. | | This table is generated automatically from the data in the actual articles. |
| If a microprocessor is missing from the list, an appropriate article for it needs to be | | If a microprocessor is missing from the list, an appropriate article for it needs to be |
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| * AMD 'Tech Day', February 22, 2017 | | * AMD 'Tech Day', February 22, 2017 |
| * AMD 2017 Financial Analyst Day, May 16, 2017 | | * AMD 2017 Financial Analyst Day, May 16, 2017 |
− |
| |
− | == References ==
| |
− | <references>
| |
− | <ref name="amd-psf">{{cite techdoc|title=White Paper: Security Analysis of AMD Predictive Store Forwarding|url=https://www.amd.com/system/files/documents/security-analysis-predictive-store-forwarding.pdf|publ=AMD|date=2021-03}}</ref>
| |
− | <ref name="amd-24593-apm2">{{cite techdoc|title=AMD64 Architecture Programmer’s Manual Volume 2: System Programming|url=https://www.amd.com/system/files/TechDocs/24593.pdf|publ=AMD|pid=24593|rev=3.37|date=2021-03}}</ref>
| |
− | <ref name="amd-24594-apm3">{{cite techdoc|title=AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System Instructions|url=https://www.amd.com/system/files/TechDocs/24594.pdf|publ=AMD|pid=24594|rev=3.32|date=2021-03}}</ref>
| |
− | <ref name="amd-26568-apm4">{{cite techdoc|title=AMD64 Architecture Programmer’s Manual Volume 4: 128-Bit and 256-Bit Media Instructions|url=https://www.amd.com/system/files/TechDocs/26568.pdf|publ=AMD|pid=26568|rev=3.24|date=2020-05}}</ref>
| |
− | <ref name="amd-56375-qos">{{cite techdoc|title=AMD64 Technology Platform Quality of Service Extensions|url=https://developer.amd.com/wp-content/resources/56375.pdf|publ=AMD|pid=56375|rev=1.02|date=2020-10}}</ref>
| |
− | <ref name="amd-56665-sog-19h">{{cite techdoc|title=Software Optimization Guide for AMD Family 19h Processors (PUB)|url=https://www.amd.com/system/files/TechDocs/56665.zip|publ=AMD|pid=56665|rev=3.00|date=2020-11}}</ref>
| |
− | <ref name="amd-55898-ppr-1901-0.35">{{cite techdoc|title=Preliminary Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors|url=https://www.amd.com/system/files/TechDocs/55898_pub.zip|publ=AMD|pid=55898|rev=0.35|date=2021-02-05}}</ref>
| |
− | <ref name="amd-55898-ppr-1901-0.50">{{cite techdoc|title=Preliminary Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors|publ=AMD|pid=55898|rev=0.50|date=2021-05-27}}</ref>
| |
− | <ref name="amd-56178-mdg-fp6">{{cite techdoc|title=FP6 Processor Motherboard Design Guide|publ=AMD|pid=56178|rev=1.03|date=2020-01}}</ref>
| |
− | </references>
| |
| | | |
| == See Also == | | == See Also == |
− | * AMD {{\\|Zen}}, {{\\|Zen 2}}, {{\\|Zen 4}} | + | * AMD {{\\|Zen}} |
| * Intel {{intel|Tigerlake|l=arch}} | | * Intel {{intel|Tigerlake|l=arch}} |
| * Read also: [https://www.anandtech.com/print/16214/amd-zen-3-ryzen-deep-dive-review-5950x-5900x-5800x-and-5700x-tested AMD Zen 3 Ryzen Deep Dive Review] | | * Read also: [https://www.anandtech.com/print/16214/amd-zen-3-ryzen-deep-dive-review-5950x-5900x-5800x-and-5700x-tested AMD Zen 3 Ryzen Deep Dive Review] |
| * Read here: [https://techmotherboard.com/best-zen-3-cpu/ AMD Zen 3 Reviews] | | * Read here: [https://techmotherboard.com/best-zen-3-cpu/ AMD Zen 3 Reviews] |