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{{amd title|K7|arch}} | {{amd title|K7|arch}} | ||
{{microarchitecture | {{microarchitecture | ||
− | + | | name = K7 | |
− | |name=K7 | + | | designer = AMD |
− | |designer=AMD | + | | manufacturer = AMD |
− | |manufacturer=AMD | + | | introduction = June 23, 1999 |
− | |introduction=June 23, 1999 | + | | phase-out = |
− | |process=250 nm | + | | process = 250 nm |
− | |process 2=180 nm | + | | process 2 = 180 nm |
− | | | + | | cores = 1 |
− | | | + | |
− | |type=Superscalar | + | | pipeline = Yes |
− | | | + | | type = Superscalar |
− | |speculative=No | + | | type 2 = |
− | |renaming=Yes | + | | OoOE = Yes |
− | |stages min=10 | + | | speculative = No |
− | |stages max=15 | + | | renaming = Yes |
− | | | + | | isa = IA-32 |
− | |extension=MMX | + | | stages min = 10 |
− | |extension 2=Extended MMX | + | | stages max = 15 |
− | |extension 3=3DNow! | + | | issues = 3 |
− | |extension 4=Extended 3DNow! | + | |
− | |extension 5=SSE | + | | inst = Yes |
− | |l1i=64 KiB | + | | feature = |
− | |l1i desc=2-way set associative | + | | extension = MMX |
− | |l1d=64 KiB | + | | extension 2 = Extended MMX |
− | |l1d desc=2-way set associative | + | | extension 3 = 3DNow! |
− | |l2= | + | | extension 4 = Extended 3DNow! |
− | |l2 desc=16-way set associative | + | | extension 5 = SSE |
− | |core name=Spitfire | + | |
− | |core name 2=Morgan | + | | cache = Yes |
− | |core name 3=Camaro | + | | l1i = 64 KiB |
− | |core name 4=Appaloosa | + | | l1i per = |
− | |core name 5=Applebred | + | | l1i desc = 2-way set associative |
− | + | | l1d = 64 KiB | |
− | + | | l1d per = | |
− | | | + | | l1d desc = 2-way set associative |
− | |predecessor=K6-III | + | | l2 = 64 KiB |
− | |predecessor link=amd/microarchitectures/k6-iii | + | | l2 per = |
− | |successor=K8 | + | | l2 desc = 16-way set associative |
− | |successor link=amd/microarchitectures/k8 | + | | l3 = |
− | + | | l3 per = | |
− | + | | l3 desc = | |
− | + | ||
− | + | | core names = Yes | |
− | + | | core name = Spitfire | |
− | + | | core name 2 = Morgan | |
− | + | | core name 3 = Camaro | |
+ | | core name 4 = Appaloosa | ||
+ | | core name 5 = Applebred | ||
+ | |||
+ | | succession = Yes | ||
+ | | predecessor = K6-III | ||
+ | | predecessor link = amd/microarchitectures/k6-iii | ||
+ | | successor = K8 | ||
+ | | successor link = amd/microarchitectures/k8 | ||
}} | }} | ||
− | '''K7''' was the [[microarchitecture]] for [[AMD]]'s {{amd| | + | '''K7''' was the [[microarchitecture]] for [[AMD]]'s {{amd|K6-III}} line of microprocessors as a successor to the {{\\|K6-III}}. K7 was superseded by {{\\|K8}} in 2003. K7 was used for AMD's {{amd|Athlon}} and {{amd|Duron}} families of processors. |
== Codenames == | == Codenames == | ||
Line 73: | Line 81: | ||
== Process Technology == | == Process Technology == | ||
− | K7 was originally manufactured on AMD's [[180 nm process]]. By late 2002 | + | K7 was originally manufactured on AMD's [[180 nm process]]. By late 2002 AMD transition to a [[130 nm process]]. |
== Architecture == | == Architecture == | ||
− | K7 was a relatively new design by [[AMD]] which marked a departure from the aging [[Socket 7]] and [[Super Socket 7]]. The new architecture introduced a number of major changes including a new | + | K7 was a relatively new design by [[AMD]] which marked a departure from the aging [[Socket 7]] and [[Super Socket 7]]. The new architecture introduced a number of major changes including a new propitiatory unified [[Socket A]]. |
=== Key changes from {{amd|K6|l=arch}} / {{amd|K6-III|l=arch}} === | === Key changes from {{amd|K6|l=arch}} / {{amd|K6-III|l=arch}} === | ||
* System Bus | * System Bus | ||
** K7 utilizes the [[Digital Alpha]] {{decc|EV6}} system bus interface | ** K7 utilizes the [[Digital Alpha]] {{decc|EV6}} system bus interface | ||
− | *** AMD licensed the technology from Digital allowing them to independently develop their own [[chipsets]] and [[motherboards]] without paying licensing | + | *** AMD licensed the technology from Digital allowing them to independently develop their own [[chipsets]] and [[motherboards]] without paying licensing frees to [[Intel]] for their [[Slot 1]] {{intel|GTL+}} bus. This does consequently meant incompatibility AMD's motherboards and Intel's motherboards. |
*** The EV6 utilizes [[double data rate]] (DDR) doubling the effective data transfer rate of the bus speed. | *** The EV6 utilizes [[double data rate]] (DDR) doubling the effective data transfer rate of the bus speed. | ||
*** 100 MHz bus = 200 [[MT/s]] | *** 100 MHz bus = 200 [[MT/s]] |
Facts about "K7 - Microarchitectures - AMD"
codename | K7 + |
core count | 1 + |
designer | AMD + |
first launched | June 23, 1999 + |
full page name | amd/microarchitectures/k7 + |
instance of | microarchitecture + |
instruction set architecture | x86-32 + |
manufacturer | AMD + |
microarchitecture type | CPU + |
name | K7 + |
pipeline stages (max) | 15 + |
pipeline stages (min) | 10 + |
process | 250 nm (0.25 μm, 2.5e-4 mm) +, 180 nm (0.18 μm, 1.8e-4 mm) + and 130 nm (0.13 μm, 1.3e-4 mm) + |