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|model number=7252 | |model number=7252 | ||
|part number=100-000000080 | |part number=100-000000080 | ||
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|market=Server | |market=Server | ||
|first announced=August 7, 2019 | |first announced=August 7, 2019 | ||
|first launched=August 7, 2019 | |first launched=August 7, 2019 | ||
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|family=EPYC | |family=EPYC | ||
|series=7002 | |series=7002 | ||
|locked=Yes | |locked=Yes | ||
− | |frequency= | + | |frequency=2,800 MHz |
|turbo frequency=3,200 MHz | |turbo frequency=3,200 MHz | ||
− | |clock multiplier= | + | |clock multiplier=28 |
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
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|core name=Rome | |core name=Rome | ||
|core family=23 | |core family=23 | ||
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− | |||
|process=7 nm | |process=7 nm | ||
|process 2=14 nm | |process 2=14 nm | ||
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|core count=8 | |core count=8 | ||
|thread count=16 | |thread count=16 | ||
+ | |max cpus=2 | ||
|max memory=4 TiB | |max memory=4 TiB | ||
− | |||
|tdp=120 W | |tdp=120 W | ||
|package name 1=amd,socket_sp3 | |package name 1=amd,socket_sp3 | ||
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|predecessor link=amd/epyc/7251 | |predecessor link=amd/epyc/7251 | ||
}} | }} | ||
− | '''EPYC 7252''' is a {{arch|64}} [[octa-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates | + | '''EPYC 7252''' is a {{arch|64}} [[octa-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates logic fabricated [[TSMC]] [[7 nm process]] and I/O fabricated on [[GlobalFoundries]] [[14 nm process]]. The 7252 has a TDP of 120 W with a base frequency of 2.8 GHz and a {{amd|precision boost|boost}} frequency of up to 3.2 GHz. This processor supports up to two-way [[symmetric multiprocessing|SMP]] and up to 4 TiB of eight channels DDR4-3200 memory per socket. |
== Cache == | == Cache == | ||
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|l1d break=8x32 KiB | |l1d break=8x32 KiB | ||
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
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|l2 cache=4 MiB | |l2 cache=4 MiB | ||
|l2 break=8x512 KiB | |l2 break=8x512 KiB | ||
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== Memory controller == | == Memory controller == | ||
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{{memory controller | {{memory controller | ||
|type=DDR4-3200 | |type=DDR4-3200 | ||
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}} | }} | ||
− | == Features == | + | == Features == |
{{x86 features | {{x86 features | ||
|real=Yes | |real=Yes | ||
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|amdpbod=No | |amdpbod=No | ||
}} | }} | ||
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Facts about "EPYC 7252 - AMD"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | EPYC 7252 - AMD#pcie + |
base frequency | 3,100 MHz (3.1 GHz, 3,100,000 kHz) + |
clock multiplier | 31 + |
core count | 8 + |
core family | 23 + |
core model | 49 + |
core name | Rome + |
core stepping | B0 + |
designer | AMD + |
die count | 3 + |
family | EPYC + |
first announced | August 7, 2019 + |
first launched | August 7, 2019 + |
full page name | amd/epyc/7252 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has amd amd-v technology | true + |
has amd amd-vi technology | true + |
has amd precision boost 2 | true + |
has amd secure encrypted virtualization technology | true + |
has amd secure memory encryption technology | true + |
has amd sensemi technology | true + |
has amd transparent secure memory encryption technology | true + |
has ecc memory support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, SenseMI Technology + and Precision Boost 2 + |
has locked clock multiplier | true + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
is multi-chip package | true + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
l3$ size | 64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) + |
ldate | August 7, 2019 + |
manufacturer | TSMC + and GlobalFoundries + |
market segment | Server + |
max cpu count | 2 + |
max memory | 4,194,304 MiB (4,294,967,296 KiB, 4,398,046,511,104 B, 4,096 GiB, 4 TiB) + |
max memory bandwidth | 190.7 GiB/s (195,276.8 MiB/s, 204.763 GB/s, 204,762.566 MB/s, 0.186 TiB/s, 0.205 TB/s) + |
max memory channels | 8 + |
microarchitecture | Zen 2 + |
model number | 7252 + |
name | EPYC 7252 + |
package | FCLGA-4094 + and SP3 + |
part number | 100-000000080 + and 100-100000080WOF + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 475.00 (€ 427.50, £ 384.75, ¥ 49,081.75) + |
series | 7002 + |
smp max ways | 2 + |
socket | LGA-4094 + and SP3 + |
supported memory type | DDR4-3200 + |
tdp | 120 W (120,000 mW, 0.161 hp, 0.12 kW) + |
technology | CMOS + |
thread count | 16 + |
turbo frequency | 3,200 MHz (3.2 GHz, 3,200,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |