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− | {{ | + | {{armh title|ARM1|arch}} |
{{microarchitecture | {{microarchitecture | ||
|atype=CPU | |atype=CPU | ||
|name=ARM1 | |name=ARM1 | ||
− | |designer= | + | |designer=ARM Holdings |
|manufacturer=VLSI Technology | |manufacturer=VLSI Technology | ||
|introduction=1985 | |introduction=1985 | ||
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|l1d per=Core | |l1d per=Core | ||
|successor=ARM2 | |successor=ARM2 | ||
− | |successor link= | + | |successor link=arm holdings/microarchitectures/arm2 |
+ | |pipeline=<!-- yes for following options --> | ||
+ | |OoOE=<!-- Yes or No only --> | ||
+ | |inst=Yes | ||
+ | |cache=Yes | ||
+ | |succession=Yes | ||
}} | }} | ||
− | '''ARM1''' was the first [[ARM]] microarchitecture implemented by [[Acorn Computers]] as a research and development project for the BBC Computer Literacy Project. ARM1 was introduced in [[1985]] and was extended to be used as a [[coprocessor]] in the Acorn's [[BBC Micro]] microcomputers. ARM1 was distributed as an evaluation system and was never commercialized. | + | '''ARM1''' was the first [[ARM]] microarchitecture implemented by [[ARM Holdings]] (then [[Acorn Computers]]) as a research and development project for the BBC Computer Literacy Project. ARM1 was introduced in [[1985]] and was extended to be used as a [[coprocessor]] in the Acorn's [[BBC Micro]] microcomputers. ARM1 was distributed as an evaluation system and was never commercialized. |
== History == | == History == | ||
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The first prototype tested worked on the first try, this was despite the ammeter reading no power. The prototype test board designed was faulty with a short. The chip was entirely running off the leakage from the I/Os. Designed to run at 1 W, the chip averaged under 100 mW typical power. | The first prototype tested worked on the first try, this was despite the ammeter reading no power. The prototype test board designed was faulty with a short. The chip was entirely running off the leakage from the I/Os. Designed to run at 1 W, the chip averaged under 100 mW typical power. | ||
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== Process Technology == | == Process Technology == | ||
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* Implements {{armh|ARMv1}} | * Implements {{armh|ARMv1}} | ||
* Goal 1.5x performance of the {{decc|VAX 11/780}} | * Goal 1.5x performance of the {{decc|VAX 11/780}} | ||
− | * | + | * 26-bit address space |
* Pipeline | * Pipeline | ||
** ''Very simple'' | ** ''Very simple'' | ||
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=== Block Diagram === | === Block Diagram === | ||
==== Core ==== | ==== Core ==== | ||
− | [[File:arm1 block diagram.svg | + | [[File:arm1 block diagram.svg]] |
== Core == | == Core == | ||
The ARM1 is an extremely simple 32-bit single-chip [[RISC]] microprocessor implementation with a number of [[CISC]] features. | The ARM1 is an extremely simple 32-bit single-chip [[RISC]] microprocessor implementation with a number of [[CISC]] features. | ||
=== Pipeline === | === Pipeline === | ||
− | The ARM1 utilizes a [[pipelining]] technique in order to improve performance and efficiency | + | The ARM1 utilizes a [[pipelining]] technique in order to improve performance and efficiency. The ARM1's pipeline consists of 3 states (although some instructions may take as much as 5 cycles): |
: [[File:arm1 pipeline.svg|800px]] | : [[File:arm1 pipeline.svg|800px]] | ||
− | + | ||
− | The ARM1 operates on a guaranteed non-overlapping [[two-phase clock]] which allowed for [[level-triggered]] transfer instead of [[edge-triggering]]. The two clock phases are not generated on-die but come from an external [[oscillator]]. A complete cycle on the ARM1 is therefore Φ1 + Φ2 | + | The ARM1 operates on a guaranteed non-overlapping [[two-phase clock]] which allowed for [[level-triggered]] transfer instead of [[edge-triggering]]. The two clock phases are not generated on-die but come from an external [[oscillator]]. A complete cycle on the ARM1 is therefore Φ1 + Φ2. |
==== Fetch ==== | ==== Fetch ==== | ||
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The Register Decode handles the register selection for both read ports and the write port. | The Register Decode handles the register selection for both read ports and the write port. | ||
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==== Execute ==== | ==== Execute ==== | ||
[[File:arm1 register file.svg|right|250px]] | [[File:arm1 register file.svg|right|250px]] | ||
− | The ARM1 has a [[physical register file]] of 25 {{arch|32}} registers (same as the [[architectural register file]]). Register 15 ({{arm|R15}}) is the [[Program Counter]]. 16 of the registers are visible to the user with the | + | The ARM1 has a [[physical register file]] of 25 {{arch|32}} registers (same as the [[architectural register file]]). Register 15 ({{arm|R15}}) is the [[Program Counter]]. 16 of the registers are visible to the user with the reminder only being accessible while in supervisor mode. The register file has two read ports for the operands heading to the ALU and a single write port for the ALU write-back value. Additionally there is a dedicated {{arm|R15}} read and write port. |
Each cycle two values are operated on. During clock phase 1 (''Φ1'') the values are fetched from the appropriate sources into the ALU for execution and during clock phase 2 (''Φ2''), the 32-bit ALU output is stored onto the Register File write port. | Each cycle two values are operated on. During clock phase 1 (''Φ1'') the values are fetched from the appropriate sources into the ALU for execution and during clock phase 2 (''Φ2''), the 32-bit ALU output is stored onto the Register File write port. | ||
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<div style="float: left; margin: 10px;">'''Register-Register:'''<br>[[File:arm1 reg reg.svg|300px]]</div> | <div style="float: left; margin: 10px;">'''Register-Register:'''<br>[[File:arm1 reg reg.svg|300px]]</div> | ||
<div style="float: left; margin: 10px;">'''Register-Immediate:'''<br>[[File:arm1 reg imm.svg|300px]]</div></div> | <div style="float: left; margin: 10px;">'''Register-Immediate:'''<br>[[File:arm1 reg imm.svg|300px]]</div></div> | ||
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{{clear}} | {{clear}} | ||
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===== Multi-Cycle Instruction ===== | ===== Multi-Cycle Instruction ===== | ||
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A number of ARM instructions cannot be implemented in a single cycle given the limited resources of the ARM1 (i.e., a single ALU and a single shifter). Instructions such as a store {{arm|STR}} (store register) requires calculating the effective address before it can store the data. To solve this problem, the ARM1 effectively runs the same instruction through the execute stage two to three times - in the first execute cycle is used to compute the address while the second execute stage the data store. | A number of ARM instructions cannot be implemented in a single cycle given the limited resources of the ARM1 (i.e., a single ALU and a single shifter). Instructions such as a store {{arm|STR}} (store register) requires calculating the effective address before it can store the data. To solve this problem, the ARM1 effectively runs the same instruction through the execute stage two to three times - in the first execute cycle is used to compute the address while the second execute stage the data store. | ||
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== Die Shot == | == Die Shot == | ||
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== All ARM1 Chips == | == All ARM1 Chips == | ||
− | + | {{empty section}} | |
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== References == | == References == | ||
* ARM hardware reference manual, ARM Evaluation System, Acorn OEM Products, August 1986 | * ARM hardware reference manual, ARM Evaluation System, Acorn OEM Products, August 1986 | ||
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== Documents == | == Documents == | ||
− | + | {{empty section}} |
Facts about "ARM1 - Microarchitectures - Acorn"
codename | ARM1 + |
core count | 1 + |
designer | Acorn Computers + |
first launched | 1985 + |
full page name | acorn/microarchitectures/arm1 + |
instance of | microarchitecture + |
instruction set architecture | ARMv1 + |
manufacturer | VLSI Technology + |
microarchitecture type | CPU + |
name | ARM1 + |
pipeline stages | 3 + |
process | 3,000 nm (3 μm, 0.003 mm) + |